wm8974gefl-v Wolfson Microelectronics plc, wm8974gefl-v Datasheet - Page 9

• Manufacturer Part Number: wm8974gefl-v
• Description: Mono Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics plc

Production Data
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SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
Note 1:
PLL pre-scaling and PLL N and K values should be set appropriately so that SYSCLK is no greater than 12.288MHz.
AUDIO INTERFACE TIMING – MASTER MODE
Figure 1 System Clock Timing Requirements
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, T
PARAMETER
System Clock Timing Information
MCLK cycle time
MCLK duty cycle
MCLK
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
T
SYMBOL
T
MCLKDS
MCLKY
t
MCLKL
t
MCLKY
MCLK=SYSCLK (=256fs)
t
MCLK input to PLL
MCLKH
CONDITIONS
Note 1
A
= +25
81.38
60:40
20
MIN
o
C
TYP
PD, Rev 4.5, September 2008
40:60
MAX
WM8974
UNIT
ns
ns
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