wm8974gefl-v Wolfson Microelectronics plc, wm8974gefl-v Datasheet - Page 74

• Manufacturer Part Number: wm8974gefl-v
• Description: Mono Codec With Speaker Driver
• Manufacturer: Wolfson Microelectronics plc

WM8974
w
36 (24h)
37 (25h)
38 (26h)
39 (27h)
40 (28h)
44 (2Ch)
45 (2Dh)
REGISTER
ADDRESS
2:0
8:5
4
3:0
8:6
5:0
8:0
8:0
8:3
2
1
0
8
7:4
3
2
1
0
8
7
BIT
NGTH
PLLPRESCALE
PLLN[3:0]
PLLK[23:18]
PLLK[17:9]
PLLK[8:0]
MONOATTN
SPKATTN
MBVSEL
AUXMODE
AUX2INPPGA
MICN2INPPGA
MICP2INPPGA
INPPGAZC
LABEL
000
0
1000
001100
010010011
011101001
0
1
1
0000
000
000000
0
0
0
0
0000
0
0
0
DEFAULT
ALC Noise gate threshold:
000=-39dB
001=-45dB
010=-51db
… (6dB steps)
111=-81dB
Reserved
0 = MCLK input not divided (default)
1 = Divide MCLK by 2 before input PLL
Integer (N) part of PLL input/output frequency ratio. Use
values greater than 5 and less than 13.
Reserved
Fractional (K) part of PLL1 input/output frequency ratio (treat
as one 24-digit binary number).
Fractional (K) part of PLL1 input/output frequency ratio (treat
as one 24-digit binary number).
Fractional (K) part of PLL1 input/output frequency ratio (treat
as one 24-digit binary number).
Reserved
Attenuation control for bypass path (output of input boost
stage) to mono mixer input
0 = 0dB
1 = -10dB
Attenuation control for bypass path (output of input boost
stage) to speaker mixer input
0 = 0dB
1 = -10dB
Reserved
Microphone Bias Voltage Control
0 = 0.9 * AVDD
1 = 0.65 * AVDD
Reserved
Auxiliary Input Mode
0 = inverting buffer
1 = mixer (on-chip input resistor bypassed)
Select AUX amplifier output as input PGA signal source.
0=AUX not connected to input PGA
1=AUX connected to input PGA amplifier negative terminal.
Connect MICN to input PGA negative terminal.
0=MICN not connected to input PGA
1=MICN connected to input PGA amplifier negative terminal.
Connect input PGA amplifier positive terminal to MICP or
VMID.
0 = input PGA amplifier positive terminal connected to VMID
1 = input PGA amplifier positive terminal connected to MICP
through variable resistor string
Reserved
Input PGA zero cross enable:
0=Update gain when gain register changes
1=Update gain on 1
st
zero cross after gain register write.
DESCRIPTION
PD, Rev 4.5, September 2008
Input Limiter /
Automatic Level
Control (ALC)
Master Clock and
Phase Locked Loop
(PLL)
Master Clock and
Phase Locked Loop
(PLL)
Master Clock and
Phase Locked Loop
(PLL)
Master Clock and
Phase Locked Loop
(PLL)
Master Clock and
Phase Locked Loop
(PLL)
Analogue Outputs
Analogue Outputs
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
Input Signal Path
Production Data
REFER TO
74