gal16vp8 Lattice Semiconductor Corp., gal16vp8 Datasheet - Page 13

• Manufacturer Part Number: gal16vp8
• Description: Gal High-speed E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

3-state levels are measured 0.5V from steady-state active
level.
Output Load Conditions (see figure)
Note: fmax with no feedback may be less than 1/(twh + twl). This
is to allow for a clock duty cycle of other than 50%.
f
Switching Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
max Descriptions
Test Condition
A
B
C
Note:
from measured
f
Active High
Active Low
Active High
Active Low
max with External Feedback 1/(
f
LOGIC
ARRAY
max with external feedback is calculated
f
t
LOGIC
ARRAY
su
t
max with No Feedback
su +
t
t
h
su and
500
500
500
R
1
t
REGISTER
co.
REGISTER
CLK
CLK
500
500
500
500
500
R
3ns 10% – 90%
2
t
t
GND to 3.0V
co
See Figure
su+
1.5V
1.5V
t
co)
50pF
50pF
50pF
5pF
5pF
C
L
13
FROM OUTPUT (O/Q)
UNDER TEST
*C
Note:
tracting
feedback (
is used primarily when calculating the delay from
clocking a register to a combinatorial output
(through registered feedback), as shown above.
For example, the timing from clock to a combi-
natorial output is equal to
Specifications GAL16VP8
L
f
INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
max with Internal Feedback 1/(
t
cf is a calculated value, derived by sub-
LOGIC
ARRAY
t
su from the period of fmax w/internal
t
cf = 1/
R
f
max -
2
t
+5V
cf
t
pd
t
REGISTER
su). The value of
t
cf +
CLK
R
1
t
pd.
t
su+
C *
L
t
TEST POINT
cf)
t
cf