gal16vp8 Lattice Semiconductor Corp., gal16vp8 Datasheet - Page 3

• Manufacturer Part Number: gal16vp8
• Description: Gal High-speed E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

The following discussion pertains to configuring the output logic
macrocell. It should be noted that actual implementation is accom-
plished by development software/hardware and is completely trans-
parent to the user.
There are three global OLMC configuration modes possible:
simple, complex, and registered. Details of each of these modes
is illustrated in the following pages. Two global bits, SYN and AC0,
control the mode configuration for all macrocells. The XOR bit of
Software compilers support the three different global OLMC modes
as different device types. Most compilers also have the ability to
automatically select the device type, generally based on the register
usage and output enable (OE) usage. Register usage on the device
forces the software to choose the registered mode. All combina-
torial outputs with OE controlled by the product term will force the
software to choose the complex mode. The software will choose
the simple mode only when all outputs are dedicated combinatorial
without OE control. For further details, refer to the compiler soft-
ware manuals.
When using compiler software to configure the device, the user
must pay special attention to the following restrictions in each mode.
In registered mode pin 1 and pin 10 are permanently configured
as clock and output enable, respectively. These pins cannot be con-
figured as dedicated inputs in the registered mode.
Output Logic Macrocell (OLMC)
Compiler Support for OLMC
3
each macrocell controls the polarity of the output in any of the three
modes, while the AC1 and AC2 bit of each of the macrocells controls
the input/output and totem-pole/open-drain configuration. These
two global and 24 individual architecture bits define all possible con-
figurations in a GAL16VP8. The information given on these archi-
tecture bits is only to give a better understanding of the device.
Compiler software will transparently set these architecture bits from
the pin definitions, so the user should not need to directly manipulate
these architecture bits.
In complex mode pin 1 and pin 10 become dedicated inputs and
use the feedback paths of pin19 and pin 11 respectively. Because
of this feedback path usage, pin19 and pin 11 do not have the
feedback option in this mode.
In simple mode all feedback paths of the output pins are routed
via the adjacent pins. In doing so, the two inner most pins ( pins
14 and 16) will not have the feedback option as these pins are
always configured as dedicated combinatorial output.
In addition to the architecture configurations, the logic compiler
software also supports configuration of either totem-pole or open-
drain outputs. The actual architecture bit configuration, again, is
transparent to the user with the default configuration being the
standard totem-pole output.
Specifications GAL16VP8