gal16vp8 Lattice Semiconductor Corp., gal16vp8 Datasheet - Page 15

• Manufacturer Part Number: gal16vp8
• Description: Gal High-speed E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

Circuitry within the GAL16VP8 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q out-
puts set low after a specified time (
state on the registered output pins (if they are enabled) will always
be high on power-up, regardless of the programmed polarity of the
output pins. This feature can greatly simplify state machine design
by providing a known state on power-up. The timing diagram for
power-up is shown above. Because of the asynchronous nature
Vref = 3.1V
Power-Up Reset
Input/Output Equivalent Schematics
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
FEEDBACK/EXTERNAL
Typical Input
INTERNAL REGISTER
OUTPUT REGISTER
Active Pull-up
Circuit
Vref
Q - OUTPUT
t
pr, 1 s MAX). As a result, the
CLK
Vcc
Vcc
Vcc (min.)
Vcc
15
t
pr
of system power-up, some conditions must be met to provide a valid
power-up reset of the GAL16VP8. First, the V
monotonic. Second, the clock input must be at static TTL level as
shown in the diagram during power up. The registers will reset
within a maximum of
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
Vref = 3.1V
Data
Output
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
Specifications GAL16VP8
t
su
Feedback
Tri-State
Control
t
pr time. As in normal system operation, avoid
Typical Output
Vcc
Active Pull-up
Circuit
Feedback
(To Input Buffer)
Vref
CC
rise must be
PIN
PIN