gal16vp8 Lattice Semiconductor Corp., gal16vp8 Datasheet - Page 6

• Manufacturer Part Number: gal16vp8
• Description: Gal High-speed E2 Cmos Pld Generic Array Logic?
• Manufacturer: Lattice Semiconductor Corp.

In the Complex mode, macrocells are configured as output only or
I/O functions.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 11 & 19) do not have input capability. De-
signs requiring eight I/Os can be implemented in the Registered
mode.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Complex Mode
XOR
XOR
6
All macrocells have seven product terms per output. One prod-
uct term is used for programmable output enable control. Pins 1
and 10 are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 12 through Pin 18 are configured to this function.
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1 has no effect on this mode.
- AC2=1 defines totem pole output.
- AC2=0 defines open-drain output.
- Pin 11 and Pin 19 are configured to this function.
Specifications GAL16VP8