m36p0r8070e0 STMicroelectronics, m36p0r8070e0 Datasheet
m36p0r8070e0
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m36p0r8070e0 Summary of contents
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... Security – 64bit unique device number – 2112 bit user programmable OTP Cells 100 000 program/erase cycles per block October 2007 M36P0R8070E0 FBGA TFBGA107 (ZAC) Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency – ...
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... PSRAM Configuration Register Enable (CR 2.18 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDF 2.19 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CCP 2.20 V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DDQ 2.21 V program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PPF 2.22 V ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/ M36P0R8070E0 ) . . . . . . . . . . . . . . . . . . . . . 11 ...
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... M36P0R8070E0 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contents 3/22 ...
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... List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 7. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4/22 M36P0R8070E0 ...
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... M36P0R8070E0 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. TFBGA connections (top view through package Figure 3. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 5. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 6. TFBGA107 active ball array, 0.8 mm pitch, package outline List of figures 5/22 ...
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... Description 1 Description The M36P0R8070E0 combines two memories in a multichip package: 256-Mbit multiple bank Flash memory (the M58PR256J) 128-Mbit PSRAM (the M69KB128AA). This datasheet should be read in conjunction with the M58PR256J and M69KB128AA datasheets, which are available from your local STMicroelectronics distributor. Recommended operating conditions do not allow more than one memory to be active at the same time ...
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... M36P0R8070E0 Table 1. Signal names Name (1) A0-A23 DQ0-DQ15 V DDQ V PPF V DDF V CCP WAIT NC DU Flash memory DPD F PSRAM A23 is an address input for the Flash memory component only. Address inputs ...
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... W F DQ5 DQ8 DQ2 DQ10 DQ0 DQ1 DQ3 DQ12 G F DQ9 DQ11 DQ4 NC V CCP DDF DDQ M36P0R8070E0 DPD F DU A21 A11 NC K A22 A12 A9 A13 E P A10 A15 A20 A8 A14 A16 NC DQ13 WAIT ...
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... M36P0R8070E0 2 Signal descriptions See Figure 1: Logic diagram connected to this device. 2.1 Address inputs (A0-A23) Addresses A0-A22 are common inputs for the Flash memory and PSRAM components. Address A23 is an input for the Flash memory component only. The address inputs select the cells in the Flash memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the Flash memory’ ...
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... lock-down is enabled and the protection status of the locked-down After Reset, all blocks are in the locked state and DD2 M36P0R8070E0 , and Reset is High the Flash memory are deselected, the , lock-down is disabled and IH , the device is in normal operation the IH , the ...
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... M36P0R8070E0 2.11 Flash Deep Power-Down (DPD The deep power-down input put sthe device in deep power-down mode. When the device is in standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting the deep power-down input causes the memory to enter deep power-down mode. ...
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... PPF it acts as a power supply pin. In this condition V PPH decoupled with a 0.1 µF ceramic capacitor close to the pin PPF circuit. The PCB track widths should be program and erase currents. PPF M36P0R8070E0 is seen as a control input. In this PPF PPF ) and the DDF must be ...
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... M36P0R8070E0 3 Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: E and E for the PSRAM. P Recommended operating conditions do not allow more than one device to be active at a time. The most common example is a simultaneous read operations on the Flash memory and the PSRAM which results in a data bus contention ...
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... IL Low Low Low Hi Hi during Deep Power-Down mode. IH M36P0R8070E0 A0- A18- A17 ( A19 A20- A22 PSRAM must be disabled. time. Any PSRAM mode is allowed Valid ...
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... M36P0R8070E0 4 Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Input pulse voltages Input and output timing ref. voltages 1. Referenced CCP DDQ Figure 4. AC measurement I/O waveform 16/22 conditions. Designers should check that the Parameter ) DDQ 0V M36P0R8070E0 Flash memory PSRAM Min Max Min 1.7 1.95 – – – 1.7 1.7 1.95 1.7 8.5 9.5 – –0.4 V +0.4 – DDQ ...
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... M36P0R8070E0 Figure 5. AC measurement load circuit 1. V means V DD DDF Table 5. Capacitance Symbol OUT 1. Sampled only, not 100% tested. V DDQ V DD DEVICE UNDER TEST 0.1µF 0.1µ includes JIG capacitance = V . CCP (1) Parameter Test Condition Input capacitance V IN Output capacitance V OUT ...
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... The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ECOPACK specifications are available at: www.st.com. Figure 6. TFBGA107 active ball array, 0.8 mm pitch, package outline Drawing is not to scale. 18/ BALL "B1" M36P0R8070E0 e ddd TFBGA-Z2 ...
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... M36P0R8070E0 Table 6. Stacked TFBGA107 active ball array, 0.8 mm pitch, package data Symbol ddd Millimeters Typ Min Max 1.20 0.20 0.85 0.35 0.30 0.40 8.00 7.90 8.10 6.40 0.10 11.00 10.90 11.10 8.80 0.80 0.80 1.10 0.40 Package mechanical Inches Typ Min Max 0.047 0.008 0.033 0.014 0.012 0.016 0.315 0.311 0.319 0.252 ...
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... Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics sales office nearest to you. 20/22 M36 1.7 to 1.95 V DDQ M36P0R8070E0 ZAC E ...
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... M36P0R8070E0 8 Revision history Table 8. Document revision history Date 2-Oct-2007 Revision 1 Initial release. Revision history Changes 21/22 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 22/22 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com M36P0R8070E0 ...