m36p0r8070e0 STMicroelectronics, m36p0r8070e0 Datasheet - Page 10

• Manufacturer Part Number: m36p0r8070e0
• Description: 256 Mbit X16, Multiple Bank, Multilevel, Burst Flash Memory 128 Mbit Burst Psram, 1.8 V Supply, Multichip Package
• Manufacturer: STMicroelectronics

Signal descriptions
2.5
2.6
2.7
2.8
2.9
2.10
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Wait (WAIT)
WAIT is an output pin common to the Flash memory and PSRAM components. However,
the WAIT signal does not behave in the same way for the PSRAM and the Flash memory.
For details on this signal, please refer to the M69KB128AA datasheet for the PSRAM and to
the M58PR256J datasheet for the Flash memory.
Flash Chip Enable input (E
The Chip Enable input activates the control logic, input buffers, decoders, and sense
amplifiers of the Flash memory. When Chip Enable is Low, V
device is in active mode. When Chip Enable is at V
outputs are high impedance and the power consumption is reduced to the standby level.
It is not allowed to have E
component can be enabled at a time.
Flash Output Enable inputs (G
The Output Enable input controls the data outputs during Flash memory bus read
operations.
Flash Write Enable (W
The Write Enable input controls the bus write operation of the Flash memory command
interface. The data and address inputs are latched on the rising edge of Chip Enable or
Write Enable, whichever occurs first.
Flash Write Protect (WP
Write Protect is an input that provides additional hardware protection for each block. When
Write Protect is Low, V
blocks cannot be changed. When Write Protect is at High, V
the locked-down blocks can be locked or unlocked. (See the lock status table in the
M58PR256J datasheet).
Flash Reset (RP
The Reset input provides a hardware reset of the Flash memories. When Reset is at V
memory is in reset mode: the outputs are high impedance and the current consumption is
reduced to the Reset supply current I
the Configuration Register is reset. When Reset is at V
Upon exiting reset mode the device enters asynchronous read mode, but a negative
transition of Chip Enable or Latch Enable is required to ensure valid data outputs.
The Reset pin can be interfaced with 3 V logic without any additional circuitry, and can be
tied to V
RPH
.
IL
, lock-down is enabled and the protection status of the locked-down
F
F
)
at V
IL
F
and E
)
F
DD2
)
P
F
. After Reset, all blocks are in the locked state and
at V
)
IL
F
)
at the same time. Only one memory
IH
the Flash memory are deselected, the
IH
, the device is in normal operation.
IH
IL
, lock-down is disabled and
, and Reset is High, V
M36P0R8070E0
IH
IL
, the
, the