m36p0r8070e0 STMicroelectronics, m36p0r8070e0 Datasheet - Page 11

• Manufacturer Part Number: m36p0r8070e0
• Description: 256 Mbit X16, Multiple Bank, Multilevel, Burst Flash Memory 128 Mbit Burst Psram, 1.8 V Supply, Multichip Package
• Manufacturer: STMicroelectronics

M36P0R8070E0
2.11
2.12
2.13
2.14
2.15
2.16
2.17
Flash Deep Power-Down (DPD
The deep power-down input put sthe device in deep power-down mode.
When the device is in standby mode and the Enhanced Configuration Register bit ECR15 is
set, asserting the deep power-down input causes the memory to enter deep power-down
mode.
When the device is in the deep power-down mode, the memory cannot be modified and the
data is protected.
The polarity of the DPD
Low by default.
PSRAM Chip Enable input (E
The Chip Enable input activates the PSRAM when driven Low (asserted). When de-
asserted (V
deep power-down mode, according to the RCR (Refresh Configuration Register) setting.
PSRAM Write Enable (W
Write Enable, W
device is in write mode and write operations can be performed either to the configuration
registers or to the memory array.
PSRAM Output Enable (G
When held Low, V
PSRAM Upper Byte Enable (UB
The Upper Byte Enable, UB
DQ15) to or from the upper part of the selected address during a write or read operation.
PSRAM Lower Byte Enable (LB
The Lower Byte Enable, LB
DQ7) to or from the lower part of the selected address during a write or read operation.
If both LB
transmitting data. Although the device seems to be deselected, it remains in an active mode
as long as E
PSRAM Configuration Register Enable (CR
When this signal is driven High, V
the RCR or the BCR (Bus Configuration Register) according to the value of A19.
P
IH
and UB
P
), the device is disabled, and goes automatically in low-power standby mode or
remains Low.
P
, controls the bus write operation of the PSRAM. When asserted (V
IL
P
, the Output Enable, G
are disabled (High), the device disables the data bus from receiving or
F
pin is determined by ECR14. The deep power-down input is active
P
P
, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-
, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-
IH
, bus read or write operations access either the value of
P
)
P
)
P
, enables the bus read operations of the PSRAM.
P
)
F
)
P
P
)
)
P
)
Signal descriptions
IL
), the
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