k9f1216u0a-ycb0 Samsung Semiconductor, Inc., k9f1216u0a-ycb0 Datasheet - Page 14

• Manufacturer Part Number: k9f1216u0a-ycb0
• Description: 512mb/256mb 1.8v Nand Flash Errata
• Manufacturer: Samsung Semiconductor, Inc.

K9F1208U0A-VCB0,VIB0,FCB0,FIB0
K9F1208Q0A-DCB0,DIB0,HCB0,HIB0
K9F1208U0A-YCB0,YIB0,PCB0,PIB0
K9F1208U0A-DCB0,DIB0,HCB0,HIB0
VALID BLOCK
NOTE :
1. The
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3.
AC TEST CONDITION
(K9F12XXX0A-XCB0 :TA=0 to 70 C, K9F12XXX0A-XIB0:TA=-40 to 85 C
CAPACITANCE
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
NOTE : 1. X can be V
Program / Erase Characteristics
K9F12XXQ0A : Vcc=1.70V~1.95V , K9F12XXU0A : Vcc=2.7V~3.6V unless otherwise noted)
Valid Block Number
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
K9F12XXQ0A:Output Load (VccQ:1.8V +/-10%)
K9F12XXU0A:Output Load (VccQ:3.0V +/-10%)
K9F12XXU0A:Output Load (VccQ:3.3V +/-10%)
Input/Output Capacitance
Input Capacitance
Program Time
Dummy Busy Time for Multi Plane Program
Number of Partial Program Cycles
in the Same Page
Block Erase Time
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
CLE
H
H
X
X
X
X
X
L
L
L
L
L
K9F12XXX0A
2. WP should be biased to CMOS high or CMOS low for standby.
Parameter
ALE
X
H
H
X
X
X
X
L
L
L
L
L
Item
(1)
IL
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks
Parameter
or V
(
T
CE
IH.
Parameter
X
X
X
X
H
A
L
L
L
L
L
L
L
=25 C, V
WE
H
H
X
X
X
X
X
CC
=1.8V/3.3V, f=1.0MHz)
Symbol
Symbol
N
C
C
I/O
VB
IN
RE
Spare Array
H
H
H
H
H
H
H
X
X
X
X
Main Array
K9F1216Q0A-DCB0,DIB0,HCB0,HIB0
K9F1216U0A-YCB0,YIB0,PCB0,PIB0
K9F1216U0A-DCB0,DIB0,HCB0,HIB0
0V/V
WP
H
H
H
H
H
X
X
X
X
X
L
Test Condition
CC
1 TTL GATE and CL=30pF
(2)
V
V
4,026
During Read(Busy) on K9F12XXX0A-Y,P or K9F1208U0A-V,F
During Read(Busy) on the devices except K9F12XXX0A-Y,P and
K9F1208U0A-V,F
IN
Data Input
Data Output
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
IL
Min
Symbol
=0V
=0V
t
t
t
Read Mode
Write Mode
PROG
K9F12XXQ0A
Nop
DBSY
BERS
13
0V to VccQ
VccQ/2
5ns
-
Min
Command Input
Address Input(4clock)
Command Input
Address Input(4clock)
-
-
-
-
Typ.
Min
-
-
-
Mode
Typ
200
1
2
-
-
1 TTL GATE and CL=100pF
1 TTL GATE and CL=50pF
FLASH MEMORY
4,096
Max
Max
10
10
K9F12XXU0A
0.4V to 2.4V
Max
500
10
1
2
3
1.5V
5ns
.
Do not erase or
Blocks
Unit
Unit
pF
pF
cycles
cycle
Unit
ms
s
s