k9f1216u0a-ycb0 Samsung Semiconductor, Inc., k9f1216u0a-ycb0 Datasheet - Page 36

• Manufacturer Part Number: k9f1216u0a-ycb0
• Description: 512mb/256mb 1.8v Nand Flash Errata
• Manufacturer: Samsung Semiconductor, Inc.

K9F1208U0A-VCB0,VIB0,FCB0,FIB0
K9F1208Q0A-DCB0,DIB0,HCB0,HIB0
K9F1208U0A-YCB0,YIB0,PCB0,PIB0
K9F1208U0A-DCB0,DIB0,HCB0,HIB0
R/B
I/O
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase
Setup command(60h). Only address A
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 12 details the sequence.
Multi-Plane Page Program
Figure 13. Four-Plane Page Program
Figure 12. Block Erase Operation
Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Since
the device is equipped with four memory planes, activating the four sets of 528 byte page registers enables a simultaneous program-
ming of four pages. Partial activation of four planes is also permitted.
After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming
process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate
71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set
of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane,
actual True Page Program (10h) instead of dumy Page Program command (11h) must be followed to start the programming process.
The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages are programmed simulta-
neously, pass/fail status is available for each page when the program operation completes. The extended status bits (I/O1 through I/
O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1" when any of the pages fails.
Multi-Plane page Program with "01h" pointer is not supported, thus prohibited.
Data
Input
R/B
I/O
X
X
80h
80h
528 bytes(x8 device)
or 264words(x16 device)
A
60h
0
~ A
Block 4088
Block 4092
Plane 0
(1024 Block)
Data Input
Address &
Block 0
Block 4
7
& A
9
~ A
Block Add. : A
Address Input(3Cycle)
25
11h
t
11h
DBSY
14
80h
80h
14
to A
~ A
25
25
is valid while A
Plane 1
(1024 Block)
Block 4093
Block 4089
Data Input
K9F1216Q0A-DCB0,DIB0,HCB0,HIB0
K9F1216U0A-YCB0,YIB0,PCB0,PIB0
K9F1216U0A-DCB0,DIB0,HCB0,HIB0
Address &
Block 1
Block 5
D0h
t
11h
11h
DBSY
9
to A
35
80h
80h
13
t
BERS
is ignored. The Erase Confirm command(D0h) following the
Block 4094
Block 4090
Data Input
Plane 2
(1024 Block)
Address &
Block 2
Block 6
70h
11h
11h
t
DBSY
80h
80h
FLASH MEMORY
Plane 3
(1024 Block)
Block 4095
Block 4091
Data Input
Address &
Block 3
Block 7
Fail
I/O
0
10h
10h
t
PROG
Pass
71h