k9f1216u0a-ycb0 Samsung Semiconductor, Inc., k9f1216u0a-ycb0 Datasheet - Page 8

• Manufacturer Part Number: k9f1216u0a-ycb0
• Description: 512mb/256mb 1.8v Nand Flash Errata
• Manufacturer: Samsung Semiconductor, Inc.

K9F1208U0A-VCB0,VIB0,FCB0,FIB0
K9F1208Q0A-DCB0,DIB0,HCB0,HIB0
K9F1208U0A-YCB0,YIB0,PCB0,PIB0
K9F1208U0A-DCB0,DIB0,HCB0,HIB0
PIN DESCRIPTION
NOTE : Connect all V
(K9F1208X0A)
(K9F1216X0A)
I/O
Pin Name
I/O
Do not leave V
0
VccQ
DNU
0
CLE
ALE
WE
WP
R/B
Vcc
Vss
N.C
CE
RE
~ I/O
~ I/O
15
7
CC
CC
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The
I/O pins float to high-z when the chip is deselected or when the outputs are disabled.
I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper-
ation, I/O8 ~ I/O15 are not used to input command & address. I/O8 ~ I/O15 are used only for data input and
output.
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase opertion. Regarding CE control during read
operation, refer to ’ Page read’ section of Device operation .
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
OUTPUT BUFFER POWER
V
VccQ is internally connected to Vcc, thus should be biased to Vcc.
POWER
V
GROUND
NO CONNECTION
Lead is not internally connected.
DO NOT USE
Leave it disconnected.
and V
or V
CC
CC
Q is the power supply for Output Buffer.
is the power supply for device.
SS
SS
disconnected.
pins of each device to common power supply outputs.
K9F1216Q0A-DCB0,DIB0,HCB0,HIB0
K9F1216U0A-YCB0,YIB0,PCB0,PIB0
K9F1216U0A-DCB0,DIB0,HCB0,HIB0
7
Pin Function
FLASH MEMORY