hys64t128020eu-3s-b2 Qimonda, hys64t128020eu-3s-b2 Datasheet - Page 13
hys64t128020eu-3s-b2
Manufacturer Part Number
hys64t128020eu-3s-b2
Description
240-pin Unbuffered Ddr2 Sdram Modules Udimm Sdram
Manufacturer
Qimonda
Datasheet
1.HYS64T128020EU-3S-B2.pdf
(91 pages)
- Current page: 13 of 91
- Download datasheet (6Mb)
Rev. 1.01, 2008-01
10202006-L0SM-FEYT
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Abbreviation
SSTL
LV-CMOS
CMOS
OD
Description
Standard input-only pin. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding pin has 2 operational states, active low and tri-state,
and allows multiple devices to share as a wire-OR.
13
HYS[64/72]T[32/64/128]xxxEU-[25F/2.5/3/3S/3.7]-B2
Unbuffered DDR2 SDRAM Module
Abbreviations for Buffer Type
Abbreviations for Pin Type
Internet Data Sheet
TABLE 6
TABLE 7
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