hys64t128020eu-3s-b2 Qimonda, hys64t128020eu-3s-b2 Datasheet - Page 5

• Manufacturer Part Number: hys64t128020eu-3s-b2
• Description: 240-pin Unbuffered Ddr2 Sdram Modules Udimm Sdram
• Manufacturer: Qimonda

1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400E–555–12–G0" where 6400E
Rev. 1.01, 2008-01
10202006-L0SM-FEYT
Product Type
HYS64T128020EU–3–B2
HYS72T64900EU–3–B2
HYS64T64900EU–3–B2
HYS72T64000EU–3–B2
HYS64T64000EU–3–B2
HYS64T32900EU–3–B2
HYS64T32000EU–3–B2
PC2-5300 (5-5-5)
HYS72T128920EU–3S–B2
HYS64T128920EU–3S–B2
HYS72T128020EU–3S–B2
HYS64T128020EU–3S–B2
HYS72T64900EU–3S–B2
HYS64T64900EU–3S–B2
HYS72T64000EU–3S–B2
HYS64T64000EU–3S–B2
HYS64T32900EU–3S–B2
HYS64T32000EU–3S–B2
PC2-4200 (4-4-4)
HYS72T128920EU–3.7–B2
HYS64T128920EU–3.7–B2
HYS72T128020EU–3.7–B2
HYS64T128020EU–3.7–B2
HYS72T64900EU–3.7–B2
HYS64T64900EU–3.7–B2
HYS72T64000EU–3.7–B2
HYS64T64000EU–3.7–B2
HYS64T32900EU–3.7–B2
HYS64T32000EU–3.7–B2
DIMM
Density
1GB
1GB
means Unbuffered DIMM modules with 6.40 GB/sec Module Bandwidth and "555–12" means Column Address Strobe (CAS) latency =5,
Row Column Delay (RCD) latency = 5 and Row Precharge (RP) latency = 5 using the latest JEDEC SPD Revision 1.2 and produced on
the Raw Card "G".
1)
Module
Organization
128M × 72
128M × 64
Compliance Code
1GB 2R×8 PC2–5300U–444–12–E0
512MB 1R×8 PC2–5300E–444–12–F0
512MB 1R×8 PC2–5300U–444–12–D0
512MB 1R×8 PC2–5300E–444–12–F0
512MB 1R×8 PC2–5300U–444–12–D0
256MB 1R×16 PC2–5300U–444–12–C1
256MB 1R×16 PC2–5300U–444–12–C1
1GB 2R×8 PC2–5300E–555–12–G0
1GB 2R×8 PC2–5300U–555–12–E0
1GB 2R×8 PC2–5300E–555–12–G0
1GB 2R×8 PC2–5300U–555–12–E0
512MB 1R×8 PC2–5300E–555–12–F0
512MB 1R×8 PC2–5300U–555–12–D0
512MB 1R×8 PC2–5300E–555–12–F0
512MB 1R×8 PC2–5300U–555–12–D0
256MB 1R×16 PC2–5300U–555–12–C1
256MB 1R×16 PC2–5300U–555–12–C1
1GB 2R×8 PC2–4200E–444–12–G0
1GB 2R×8 PC2–4200U–444–12–E0
1GB 2R×8 PC2–4200E–444–12–G0
1GB 2R×8 PC2–4200U–444–12–E0
512MB 1R×8 PC2–4200E–444–12–F0
512MB 1R×8 PC2–4200U–444–12–D0
512MB 1R×8 PC2–4200E–444–12–F0
512MB 1R×8 PC2–4200U–444–12–D0
256MB 1R×16 PC2–4200U–444–12–C1
256MB 1R×16 PC2–4200U–444–12–C1
Memory
Ranks
2
2
2)
ECC/
Non-ECC
ECC
Non-ECC
5
HYS[64/72]T[32/64/128]xxxEU-[25F/2.5/3/3S/3.7]-B2
18
16
# of SDRAMs # of row/bank/column
Description
2 Ranks, Non-ECC 512Mbit (×8)
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
2 Ranks, Non-ECC 512Mbit (×8)
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
1 Rank, Non-ECC
Unbuffered DDR2 SDRAM Module
bits
14/2/10
14/2/10
SDRAM Technology
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×8)
512Mbit (×16)
512Mbit (×16)
Internet Data Sheet
Address Format
TABLE 3
Raw
Card
G
E