MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet
MSC8101UG/D
Related parts for MSC8101UG/D
MSC8101UG/D Summary of contents
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Freescale Semiconductor Technical Data MSC8103 Network Digital Signal Processor CPM 3 × FCC UTOPIA Interface 2 × MCC MII 4 × SCC • × SMC TDMs • • SPI I2C Other Peripherals Extended Core Address Program Register Sequencer ...
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Table of Contents MSC8103 Features .................................................................................................................................................................................... iii Target Applications .....................................................................................................................................................................................iv Product Documentation ..............................................................................................................................................................................iv Chapter 1 Signals/Connections 1.1 Power Signals......................................................................................................................................................................... 1-4 1.2 Clock Signals ......................................................................................................................................................................... 1-4 1.3 Reset, Configuration, and EOnCE Event Signals .................................................................................................................. 1-5 1.4 System Bus, HDI16, and Interrupt ...
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MSC8103 Features • SC140 core — Architecture optimized for efficient C/C++ code compilation — Four 16-bit ALUs and two 32-bit AGUs — 1200 DSP MMACS running at 300 MHz — Very low power dissipation — Variable-length execution set (VLES) execution ...
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... Detailed description of the SC140 family processor core and instruction set Application Notes Documents describing specific applications or optimized device operation including code examples MSC8103 Network Digital Signal Processor, Rev Table 1. MSC8103 Documentation Description Order Number MSC8103/D MSC8101UG/D MSC8103RM/D MNSC140CORE/D See the MSC8103 product website Freescale Semiconductor ...
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Signals/Connections The MSC8103 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and Figure 1-2. Table 1-1 lists the functional groups, states the number of signal connections in each group, and references the table that ...
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Signals/Connections VCCSYN1 GNDSYN1 For the signals PB[31–18] multiplexed on Ports A–D, see Figure 1-2 PC[31–22, 15–12, 7–4] PD[31–29, 19–16, 7] EOnCE Event Configuration EED EE0 EE1 EE[2–3] EE[4–5] BTM[0–1] PORESET RSTCONF BNK- TC[0–2] MODCK[1–3] SEL[0–2] THERM[1–2] SPARE1, SPARE5 Note: Refer ...
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FCC1 ATM/UTOPIA FCC1 MPHY MPHY Master HDLC/ Master HDLC Ethernet mux poll transp. dir. poll MII or Slave Serial Nibble COL TXENB TXCLAV TXCLAV0 CRS RTS TXSOC (master) TX_ER RXENB TX_EN RXSOC RX_DV (slave) RXCLAV RXCLAV0 RX_ER TXD0 TXD1 TXD2 ...
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Signals/Connections 1.1 Power Signals Table 1-2. Power Name V Internal Logic Power DD V dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with DD an extremely low impedance path to ...
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Signal Name Type CLKOUT Output Clock Out The system bus clock. DLLIN Input DLLIN Synchronizes with an external device. Note: 1.3 Reset, Configuration, and EOnCE Event Signals Table 1-4. Signal Name Type DBREQ Input Debug Request Determines whether to go ...
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Signals/Connections Table 1-4. Reset, Configuration, and EOnCE Event Signals (Continued) Signal Name Type BTM[0–1] Input Boot Mode 0–1 Determines the MSC8103 boot mode when PORESET is deasserted. See the emulation and debug chapter in the SC140 DSP Core Reference Manual ...
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Although there are eight interrupt request ( that can connect to these internal signal lines. After reset, the default configuration includes two input lines. The designer must select one line for each required interrupt and reconfigure the other external signal ...
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Signals/Connections Table 1-5. Signal Data Flow BR Input/Output Bus Request Output An output when an external arbiter is used. The MSC8103 asserts this pin to request ownership of the bus. Input An input when an internal arbiter is used. An ...
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Table 1-5. Signal Data Flow D[32–47] Input/Output Data Bus Bits 32–47 In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. HD[0–15] Input/Output Host Data ...
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Signals/Connections Table 1-5. Signal Data Flow D56 Input/Output Data Bus Bit 56 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HACK/HACK Output Host ...
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Table 1-5. Signal Data Flow IRQ1 Input Interrupt Request 1 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP1 Input/Output Data Parity 1 The agent that drives the ...
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Signals/Connections Table 1-5. Signal Data Flow IRQ5 Input Interrupt Request 5 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP5 Input/Output Data Parity 5 The agent that drives ...
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Table 1-5. Signal Data Flow IRQ7 Input Interrupt Request 7 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. INT_OUT Output Interrupt Output Driven from the MSC8103 internal interrupt ...
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Signals/Connections Table 1-6. Signal Data Flow PSDA10 Output Bus SDRAM A10 Output from the bus SDRAM controller. This pin is part of the address when a row address is driven part of the command when a column address ...
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CPM Ports The MSC8103 CPM supports the subset of MPC8260 signals as described below. • The MSC8103 CPM includes the following set of communication controllers: • Two full-duplex fast serial communications controllers (FCCs) that support: — Asynchronous transfer mode ...
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Signals/Connections 1.6.1 Port A Signals Name Peripheral Controller: General- Dedicated Signal Purpose I/O Protocol PA31 FCC1: TXENB UTOPIA master FCC1: TXENB UTOPIA slave FCC1: COL MII PA30 FCC1: TXCLAV UTOPIA slave FCC1: TXCLAV UTOPIA master , or FCC1: TXCLAV0 UTOPIA ...
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Name Peripheral Controller: General- Dedicated Signal Purpose I/O Protocol PA27 FCC1: RXSOC UTOPIA slave FCC1: RX_DV MII PA26 FCC1: RXCLAV UTOPIA slave FCC1: RXCLAV UTOPIA master, or RXCLAV0 UTOPIA master, Multi-PHY, direct polling FCC1: RX_ER MII PA25 FCC1: TXD0 UTOPIA ...
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Signals/Connections Name Peripheral Controller: General- Dedicated Signal Purpose I/O Protocol PA22 FCC1: TXD3 UTOPIA PA21 FCC1: TXD4 UTOPIA FCC1: TXD3 MII and HDLC nibble PA20 FCC1: TXD5 UTOPIA FCC1: TXD2 MII and HDLC nibble PA19 FCC1: TXD6 UTOPIA FCC1: TXD1 ...
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Name Peripheral Controller: General- Dedicated Signal Purpose I/O Protocol PA17 FCC1: RXD7 UTOPIA FCC1: RXD0 MII and HDLC nibble FCC1: RXD HDLC serial and transparent PA16 FCC1: RXD6 UTOPIA FCC1: RXD1 MII and HDLC nibble PA15 FCC1: RXD5 UTOPIA RXD2 ...
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Signals/Connections Name Peripheral Controller: General- Dedicated Signal Purpose I/O Protocol PA12 FCC1: RXD2 UTOPIA SDMA: MSNUM3 PA11 FCC1: RXD1 UTOPIA SDMA: MSNUM4 PA10 FCC1: RXD0 UTOPIA SDMA: MSNUM5 PA9 SMC2: SMTXD SI1 TDMA1: L1TXD0 TDM nibble PA8 SMC2: SMRXD SI1 ...
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Name Peripheral Controller: General- Dedicated Signal Purpose I/O Protocol PA7 SMC2: SMSYN SI1 TDMA1: L1TSYNC TDM nibble and TDM serial PA6 SI1 TDMA1: L1RSYNC TDM nibble and TDM serial 1.6.2 Port B Signals Name Peripheral Controller: General- Dedicated I/O Purpose ...
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Signals/Connections Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PB28 FCC2: RTS HDLC serial , HDLC nibble , and transparent FCC2: RX_ER MII SCC2: RTS, TENA SI2 TDMB2: L1TSYNC TDM serial PB27 FCC2: COL MII SI2 TDMC2: L1TXD TDM ...
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Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PB23 FCC2: TXD1 MII and HDLC nibble SI1 TDMA1: L1RXD2 TDM nibble SI2 TDMD2: L1TXD TDM serial PB22 FCC2: TXD0 MII and HDLC nibble FCC2: TXD HDLC serial and transparent SI1 ...
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Signals/Connections Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PB18 FCC2: RXD3 MII and HDLC nibble SCL 1.6.3 Port C Signals Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PC31 BRG1O CLK1 TIMER1/2: TGATE1 MSC8103 ...
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Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PC30 BRG2O CLK2 Timer1: TOUT1 EXT1 PC29 BRG3O CLK3 TIN2 SCC1: CTS, CLSN MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor Table 1-9. Port C Signals (Continued) Dedicated I/O Data ...
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Signals/Connections Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PC28 BRG4O CLK4 TIN1 Timer2: TOUT2 SCC2: CTS, CLSN PC27 BRG5O CLK5 TIMER3/4: TGATE2 MSC8103 Network Digital Signal Processor, Rev. 11 1-26 Table 1-9. Port C Signals (Continued) Dedicated I/O ...
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Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PC26 BRG6O CLK6 Timer3: TOUT3 TMCLK PC25 BRG7O CLK7 TIN4 DMA: DACK2 MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor Table 1-9. Port C Signals (Continued) Dedicated I/O Data Direction ...
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Signals/Connections Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PC24 BRG8O CLK8 TIN3 Timer4: TOUT4 DMA: DREQ2 PC23 CLK9 DMA: DACK1 EXT2 MSC8103 Network Digital Signal Processor, Rev. 11 1-28 Table 1-9. Port C Signals (Continued) Dedicated I/O Data ...
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Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PC22 SI1: L1ST1 CLK10 DMA: DREQ1 PC15 SMC2: SMTXD SCC1: CTS/CLSN FCC1: TXADDR0 UTOPIA master FCC1: TXADDR0 UTOPIA slave PC14 SI1: L1ST2 SCC1: CD, RENA FCC1: RXADDR0 UTOPIA master FCC1: RXADDR0 ...
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Signals/Connections Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PC13 SI1: L1ST4 SCC2: CTS,CLSN FCC1:TXADDR1 UTOPIA master FCC1: TXADDR1 UTOPIA slave PC12 SI1: L1ST3 SCC2: CD, RENA FCC1: RXADDR1 UTOPIA master FCC1: RXADDR1 UTOPIA slave MSC8103 Network Digital Signal ...
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Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PC7 SI2: L1ST1 FCC1: CTS HDLC serial , HDLC nibble , and transparent FCC1: TXADDR2 UTOPIA master FCC1: TXADDR2 UTOPIA slave FCC1: TXCLAV1 UTOPIA multi-PHY master, direct polling PC6 SI2: L1ST2 ...
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Signals/Connections Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PC5 SMC1: SMTXD SI2: L1ST3 FCC2: CTS HDLC serial , HDLC nibble , and transparent PC4 SMC1: SMRXD SI2: L1ST4 FCC2: CD HDLC serial , HDLC nibble , and transparent ...
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Port D Signals Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PD31 SCC1: RXD DMA: DRACK1 DMA: DONE1 PD30 SCC1: TXD DMA: DRACK2 DMA: DONE2 PD29 SCC1: RTS, TENA FCC1: RXADDR3 UTOPIA master FCC1: RXADDR3 UTOPIA slave FCC1: ...
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Signals/Connections Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PD19 FCC1: TXADDR4 UTOPIA master FCC1: TXADDR4 UTOPIA slave FCC1: TXCLAV3 UTOPIA multi-PHY master, direct polling BRG1O SPI: SPISEL PD18 FCC1: RXADDR4 UTOPIA master FCC1: RXADDR4 UTOPIA slave FCC1: RXCLAV3 ...
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Name Peripheral Controller: General- Dedicated I/O Purpose I/O Protocol PD17 BRG2O FCC1: RXPRTY UTOPIA SPI: SPIMOSI PD16 FCC1: TXPRTY UTOPIA SPI: SPIMISO PD7 SMC1: SMSYN FCC1: TXADDR3 UTOPIA master FCC1: TXADDR3 UTOPIA slave FCC1: TXCLAV2 UTOPIA multi-PHY master, direct polling ...
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Signals/Connections 1.7 JTAG Test Access Port Signals The MSC8103 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-11. Table 1-11. Signal Name ...
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Physical and Electrical Specifications This document contains detailed information on environmental limits, power considerations, DC/AC electrical characteristics, and AC timing specifications for the MSC8103 communications processor, mask set 2K87M. For additional information, see the MSC8103 Reference Manual. 2.1 Absolute Maximum ...
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Physical and Electrical Specifications 2.2 Recommended Operating Conditions Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2-2. Rating SC140 core supply voltage PLL supply voltage I/O supply voltage Input voltage Operating ...
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DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8103. The measurements in Table 2-4 assume the following system conditions: • – 100 °C J • = 1.6 V ± ...
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Physical and Electrical Specifications 2.5 Clock Configuration The following sections provide a general description of clock configuration. 2.5.1 Valid Clock Modes Table 2-6 shows the maximum frequency values for each rated core frequency (275 or 300 MHz). The user must ...
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System Clock Control Register Bit Type Reset Bit Type Reset Figure 2-2. SCCR is memory-mapped into the SIU register map of the MSC8103. Defaults Name Bit No. PORESET Hard Reset — ...
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Physical and Electrical Specifications Defaults Name Bit No. PORESET Hard Reset COREPDF Configuration Unaffected 0–3 Pins COREMF Configuration Unaffected 4–7 Pins BUSDF Configuration Unaffected 8–11 Pins CPMDF Configuration Unaffected 12–15 Pins SPLLPDF Configuration Unaffected 16–19 Pins SPLLMF Configuration Unaffected 20–23 ...
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AC Timings The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. AC timings are based load, except where noted otherwise, and 50 Ω transmission line. 2.6.1 Output ...
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Physical and Electrical Specifications 3.3 V 1.6 V 1.06 V PORESET/TRST asserted V applied DDH Figure 2-5. Start-Up Sequence with CLKIN Started After V 3.3 V 1.6 V 1.06 V o.5 V PORESET/TRST asserted V applied DDH Figure 2-6. Start-Up ...
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Clock Input Clock SPLL MF Clock Bus/Output Serial Communications Controller Communications Processor Module SC140 Core Baud Rate Generator • For BRG • For BRG (default) • For BRG • For BRG ...
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Physical and Electrical Specifications 2.6.4.1 Reset Operation The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are ...
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No. Characteristics 4 Delay from SPLL lock to DLL lock • DLL enabled — BCLK = 18 MHz — BCLK = 75 MHz • DLL disabled 5 Delay from SPLL lock to HRESET deassertion • DLL enabled — BCLK = ...
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Physical and Electrical Specifications 1 PORESET asserted for Input min 16 CLKIN. PORESET Internal HRESET Output (I/O) SRESET Output (I/O) Figure 2-7. MSC8103 Network Digital Signal Processor, Rev. 11 2-12 RSTCONF, HPE HRM, BTM pins are sampled Any time MODCK[1–3] ...
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Hardware Reset Configuration Hardware reset configuration is enabled if while changes from assertion to deassertion determines the MSC8103 configuration. If RSTCONF PORESET is deasserted (driven high) while RSTCONF is asserted (driven low) while RSTCONF 2.6.4.4, Hardware Reset Configuration, explains ...
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Physical and Electrical Specifications 2.6.5 System Bus Access Timing 2.6.5.1 Core Data Transfers Generally, all MSC8103 bus and system output signals are driven from the rising edge of the reference clock (REFCLK), which is . Memory controller signals, however, trigger ...
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No. 10 Hold time for all signals after the 50% level of the DLLIN rising edge 11a ABB/AACK set-up time before the 50% level of the DLLIN rising edge 11b DBG/DBB/BR/TC set-up time before the 50% level of the DLLIN ...
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Physical and Electrical Specifications No. 31a TA delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode 31b TEA delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline ...
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Data bus inputs—ECC and parity modes Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL inputs Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL/BADDR[27–31] outputs AACK/ARTRY/ABB/TS/DBG/BG/BR/DBB/CS signals MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor DLLIN AACK/ARTRY/TA/TEA/DBG/BG/BR PSDVAL/ABB/DBB/TS inputs Data bus inputs—normal mode DP inputs PUPMWAIT/IRQn input PSDVAL/TEA/TA outputs Data bus outputs ...
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Physical and Electrical Specifications 2.6.5.2 DMA Data Transfers Table 2-18 describes the DMA signal timing. Number 72 DREQ set-up time before DLLIN falling edge 73 DREQ hold time after DLLIN falling edge 74 DONE set-up time before DLLIN rising edge ...
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Table 2-19. Number 48 Host data input minimum hold time after write data strobe deassertion Host data input minimum hold time after HACK write deassertion 49 Read data strobe minimum assertion to output data active from high 4 impedance HACK ...
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Physical and Electrical Specifications HA[0–3] HCS[1–2] HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 2-12. HA[0–3] HCS[1–2] HRD HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 2-13. MSC8103 Network Digital Signal Processor, Rev. 11 2-20 57 ...
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HA[0–3] HCS[1–2] HRW HDS HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 2-14. HA[0–3] HCS[1–2] HWR HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 2-15. MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor 57 58 ...
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Physical and Electrical Specifications Figure 2-16 shows Host DMA read timing. Figure 2-16. Figure 2-17 shows Host DMA write timing. (Output) HD[0–15] (Output) Figure 2-17. MSC8103 Network Digital Signal Processor, Rev. 11 2-22 HREQ (Output) 64 44a HACK RX[0–3] Read ...
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CPM Timings No. 39 FCC input set-up time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) 17 FCC input hold time after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial ...
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Physical and Electrical Specifications Serial input clock FCC inputs FCC outputs SCC/SMC/SPI/I2C inputs SCC/SMC/SPI/I2C outputs Figure 2-20. SCC/SMC/SPI/I2C inputs SCC/SMCSPI/I2C outputs Figure 2-21. Serial input clock TDM inputs TDM outputs MSC8103 Network Digital Signal Processor, Rev. 11 2-24 39b Figure ...
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PIO/TIMER/DMA inputs PIO/TIMER/DMA outputs Figure 2-23. Note: The timing values refer to minimum system timing requirements. Actual implementation requires conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and output signals associated with the ...
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Physical and Electrical Specifications TCK V (Input) IL TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) Figure 2-25. TCK (Input) TRST (Input) 512 MSC8103 Network Digital Signal Processor, Rev. 11 2-26 508 Input Data Valid 510 Output Data Valid ...
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Packaging This chapter provides information about the MSC8103 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1 are allocated. The MSC8103 is available in a 332-pin lidded flip chip-plastic ball grid array ...
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Packaging D11 A IRQ5 D10 IRQ1 B IRQ3 THERM IRQ4 DP0 1 THERM IRQ2 IRQ6 D8 D EE1 EE0 2 EE2 VDDH VDD VDDH ...
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A D62 D63 D55 D51 D60 BADDR B DBG PWE6 D50 D59 D54 28 BADDR C DBB D61 D49 D58 D53 29 D BADDR GBL PWE5 D48 D57 D52 27 MOD PSD E PSDA D56 ...
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Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 3-4 MSC8103 Signal Listing By Name Signal Name Number A0 W15 A1 N14 A2 V15 A3 T14 A4 U15 A5 W16 A6 V16 A7 W17 A8 U16 A9 V17 A10 ...
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Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number ALE ARTRY BADDR27 BADDR28 BADDR29 BADDR30 BADDR31 BCTL0 BCTL1 BG BNKSEL0 BNKSEL1 BNKSEL2 BR BRG1O BRG1O BRG2O BRG2O BRG3O BRG4O ...
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Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 3-6 MSC8103 Signal Listing By Name (Continued) Signal Name Number CLK5 CLK6 CLK7 CLK8 CLK9 CLK10 CLKIN CLKOUT COL for FCC1 COL for FCC2 CRS for FCC1 CRS for FCC2 ...
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Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 ...
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Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 3-8 MSC8103 Signal Listing By Name (Continued) Signal Name Number D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 ...
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Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number DP4 DP5 DP6 DP7 DRACK1/DONE1 DRACK2/DONE2 DREQ1 DREQ2 DREQ3 DREQ4 EE0 EE1 EE2 EE3 EE4 EE5 EED EXT_BG2 EXT_BG3 EXT_BR2 ...
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Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 3-10 MSC8103 Signal Listing By Name (Continued) Signal Name Number GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number HA2 HA3 HACK/HACK HCS1/HCS1 HCS2/HCS2 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 ...
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Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 3-12 MSC8103 Signal Listing By Name (Continued) Signal Name IRQ1 IRQ2 IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ4 IRQ5 IRQ5 IRQ6 IRQ7 IRQ7 L1RSYNC for SI1 TDMA1 L1RSYNC for SI2 TDMB2 ...
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Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name L1TXD1 for SI1 TDMA1 Nibble L1TXD2 for SI1 TDMA1 Nibble L1TXD3 for SI1 TDMA1 Nibble LIST1 for SI1 LIST1 for SI2 ...
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Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 3-14 MSC8103 Signal Listing By Name (Continued) Signal Name Number PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB18 PB19 PB20 PB21 PB22 PB23 ...
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Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number PBS6 PBS7 PC4 PC5 PC6 PC7 PC12 PC13 PC14 PC15 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 ...
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Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 3-16 MSC8103 Signal Listing By Name (Continued) Signal Name Number PGTA POE PORESET PPBS PSDA10 PSDAMUX PSDCAS PSDDQM0 PSDDQM1 PSDDQM2 PSDDQM3 PSDDQM4 PSDDQM5 PSDDQM6 PSDDQM7 PSDRAS PSDVAL PSDWE PUPMWAIT PWE0 ...
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Table 3-1. RXADDR2/RXCLAV1 for FCC1 UTOPIA 8 MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name RSTCONF RTS for FCC1 RTS for FCC2 RTS/TENA for SCC1 RTS/TENA for SCC2 RX_DV for FCC1 ...
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Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 3-18 MSC8103 Signal Listing By Name (Continued) Signal Name RXD3 for FCC2 MII/HDLC nibble RXD4 for FCC1 UTOPIA 8 RXD5 for FCC1 UTOPIA 8 RXD6 for FCC1 UTOPIA 8 RXD7 ...
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Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name TGATE1 TGATE2 THERM1 THERM2 TIN1/TOUT2 TIN2 TIN3/TOUT4 TIN4 TMCLK TMS TOUT1 TOUT3 TRST TS TSIZ0 TSIZ1 TSIZ2 TSIZ3 TT0 TT1 TT2 ...
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Packaging Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 3-20 MSC8103 Signal Listing By Name (Continued) Signal Name TXCLAV0 for FCC1 UTOPIA 8 TXCLAV1 for FCC1 UTOPIA 8 TXCLAV2 for FCC1 UTOPIA 8 TXCLAV3 for FCC1 UTOPIA 8 TXD ...
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Table 3-1. MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor MSC8103 Signal Listing By Name (Continued) Signal Name Number DDH ...
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Packaging Table 3-2. Number A10 A11 A12 A13 A14 A15 A16 A17 A18 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 ...
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Table 3-2. Number C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 ...
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Packaging Table 3-2. Number E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 G1 G2 ...
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Table 3-2. Number G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 H13 H14 H15 H16 H17 H18 H19 PA30 / ...
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Packaging Table 3-2. Number J16 J17 J18 J19 K13 K14 K15 K16 K17 K18 K19 L1 L2 PB28 / FCC2:RX_ER / FCC2:HDLC:RTS / SCC2:RTS/TENA / TDMB2:L1TSYNC L13 L14 ...
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Table 3-2. Number M7 M13 M14 M15 M16 M17 M18 M19 N10 PC6 / FCC1:UTOPIA8:RXADDR2 / FCC1:UTOPIA8:RXADDR2/RXCLAV1 / N11 N12 N13 N14 N15 N16 N17 N18 N19 ...
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Packaging Table 3-2. Number P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 ...
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Table 3-2. Number T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 PD18 / FCC1:UTOPIA8:RXADDR4 / FCC1:UTOPIA8:RXCLAV3 / SPI:SPICLK U10 U11 U12 U13 U14 U15 U16 U17 U18 ...
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Packaging Table 3-2. Number PD7 / FCC1:UTOPIA8:TXADDR3 / FCC1:UTOPIA8:TXCLAV2 / SMC1:SMSYN V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W10 W11 W12 W13 W14 W15 W16 W17 ...
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Lidded FC-PBGA Package Mechanical Drawing . Figure 3-3. Case 1473-01 Mechanical Information, 332-pin Lidded FC-PBGA Package MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor Lidded FC-PBGA Package Mechanical Drawing CASE 1473-01 Notes: 1. Dimensioning and tolerancing per ASME ...
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Packaging MSC8103 Network Digital Signal Processor, Rev. 11 3-32 Freescale Semiconductor ...
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Design Considerations This chapter includes design and layout guidelines for manufacturing boards using the MSC8103. 4.1 Thermal Design Considerations The average chip-junction temperature where = ambient temperature ° θ = package thermal resistance ...
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Design Considerations Select the bootstrap diodes such that a nominal V / power supply becomes active. In Figure 4-1, four MUR420 Schottky barrier diodes are connected CCSYN series; each has a forward voltage (V 0.9 V ...
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Since the address pins switch once at every second cycle, the address pins frequency is a quarter of the bus frequency (that is, 25 MHz). For the same reason the data pins frequency is 3.125 MHz. Number of Pins Pins ...
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Design Considerations and should be provided with an extremely low impedance path to ground and should be bypassed GND GND SYN SYN1 to and , respectively 0.01-µF capacitor located as close as possible to the chip package. The ...
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Ordering Information Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order. Supply Part Package Type Voltage MSC8103 1.6 V core Lidded Flip Chip Plastic Ball 3.3 V I/O Grid Array (FC-PBGA) How ...