MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 16

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Signals/Connections
1-12
IRQ5
DP5
DREQ4
EXT_DBG3
IRQ6
DP6
DACK3
IRQ7
DP7
DACK4
TA
TEA
NMI
NMI_OUT
PSDVAL
Signal
Input
Input/Output
Input
Output
Input
Input/Output
Output
Input
Input/Output
Output
Input/Output
Input/Output
Input
Output
Input/Output
Data Flow
Table 1-5.
MSC8103 Network Digital Signal Processor, Rev. 11
Interrupt Request 5
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Data Parity 5
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity five pin should give odd parity (odd number of ones) on the group of signals that includes data
parity 5 and D[40–47].
DMA Request 4
An external peripheral uses this pin to request DMA service.
External Data Bus Grant 3
The MSC8103 asserts this pin to grant data bus ownership to an external bus master.
Interrupt Request 6
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Data Parity 6
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity six pin should give odd parity (odd number of ones) on the group of signals that includes data
parity 6 and D[48–55].
DMA Acknowledge 3
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
Interrupt Request 7
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Data Parity 7
The master or slave that drives the data bus also drives the data parity signals. The value driven on
the data parity seven pin should give odd parity (odd number of ones) on the group of signals that
includes data parity 7 and D[56–63].
DMA Acknowledge
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
Transfer Acknowledge
Indicates that a data beat is valid on the data bus. For single beat transfers, assertion of TA
indicates the termination of the transfer. For burst transfers, TA is asserted four times to indicate the
transfer of four data beats with the last assertion indicating the termination of the burst transfer.
Transfer Error Acknowledge
Indicates a bus error. masters within the MSC8103 monitor the state of this pin. The MSC8103
internal bus monitor can assert this pin if it identifies a bus transfer that is hung.
Non-Maskable Interrupt
When an external device asserts this line, the MSC8103 NMI input is asserted.
Non-Maskable Interrupt
Driven from the MSC8103 internal interrupt controller. Assertion of this output indicates that a
non-maskable interrupt, pending in the MSC8103 internal interrupt controller, is waiting to be
handled by an external host.
Data Valid
Indicates that a data beat is valid on the data bus. The difference between the TA pin and PSDVAL
is that the TA pin is asserted to indicate data transfer terminations while the PSDVAL signal is
asserted with each data beat movement. Thus, when TA is asserted, PSDVAL is asserted, but when
PSDVAL is asserted, TA is not necessarily asserted. For example when the SDMA initiates a double
word (2x64 bits) transfer to a memory device that has a 32-bit port size, PSDVAL is asserted three
times without TA, and finally both pins are asserted to terminate the transfer.
System Bus, HDI16, and Interrupt Signals (Continued)
1
1
1
1
1
1
1
1
1
1,2
Description
Freescale Semiconductor