MSC8101UG/D FREESCALE [Freescale Semiconductor, Inc], MSC8101UG/D Datasheet - Page 23

• Manufacturer Part Number: MSC8101UG/D
• Description: Network Digital Signal Processor
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
Purpose I/O
General-
PA17
PA16
PA15
PA14
PA13
FCC1: RXD7
UTOPIA
FCC1: RXD0
MII and HDLC nibble
FCC1: RXD
HDLC serial and transparent
FCC1: RXD6
UTOPIA
FCC1: RXD1
MII and HDLC nibble
FCC1: RXD5
UTOPIA
RXD2
MII and HDLC nibble
FCC1: RXD4
UTOPIA
FCC1: RXD3
MII and HDLC nibble
FCC1: RXD3
UTOPIA
SDMA: MSNUM2
Peripheral Controller:
Name
Dedicated Signal
Protocol
MSC8103 Network Digital Signal Processor, Rev. 11
Table 1-7.
Dedicated
Direction
I/O Data
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Port A Signals (Continued)
FCC1: UTOPIA Receive Data Bit 7.
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. When no ATM data is
available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY
configurations, RXD[0–7] is tri-stated, enabled only when RXENB is
asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 0
RXD[3–0] is supported by MII and HDLC nibble mode in FCC1. RXD0 is
the least significant bit.
FCC1: HDLC Serial and Transparent Receive Data Bit
This is the single receive data bit supported by HDLC and transparent
modes.
FCC1: UTOPIA Receive Data Bit 6.
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. This is bit 6 of the receive data. RXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 1
This is bit 1 of the receive nibble data. RXD3 is the most significant bit.
FCC1: UTOPIA Receive Data Bit 5
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. This is bit 5 of the receive data. RXD7 is the most significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 2
This is bit 2 of the receive nibble data. RXD3 is the most significant bit.
FCC1: UTOPIA Receive Data Bit 4.
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant
bit. When no ATM data is available, idle cells are inserted. A cell is 53
bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated,
enabled only when RXENB is asserted.
FCC1: MII and HDLC Nibble Receive Data Bit 3
RXD3 is the most significant bit of the receive nibble bit.
FCC1: UTOPIA Receive Data Bit 3
The MSC8103 inputs ATM cell octets (UTOPIA interface data) on
RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant
bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is
tri-stated, enabled only when RXENB is asserted.
Module Serial Number Bit 2
The MSNUM has 6 bits that identify devices using the serial DMA
(SDMA) modules. MSNUM[0–4] is the sub-block code of the current
peripheral controller using SDMA. MSNUM5 indicates the section,
transmit (0) or receive (1), that is active during the transfer. The
information is recorded in the SDMA transfer error registers.
Description
CPM Ports
1-19