CYIL1SM4000AA-GWCES Cypress Semiconductor Corp., CYIL1SM4000AA-GWCES Datasheet - Page 13

• Manufacturer Part Number: CYIL1SM4000AA-GWCES
• Description: 4 Megapixel CMOS Image Sensor
• Manufacturer: Cypress Semiconductor Corp.

In case the dual slope operation is desired, you need to give a
second reset pulse to a lower reset level during integration. This
is done by the control signal Reset_ds and by the power supply
Vres_ds that defines the level to which the pixel has to be reset.
Note that Reset is dominant over Reset_ds, which means that
the high voltage level is applied for reset, if both pulses occur at
the same time.
Note that multiple slopes are possible having multiple Reset_ds
pulses with a lower Vres_ds level for each pulse given within the
same integration time
The rise and fall times of the internal generated signals are not
very fast (200 ns). In fact they are made rather slow to limit the
maximum current through the power supply lines (Vmem_h,
Vmem_l, Vres, Vres_ds, Vdd). Current limitation of those power
supplies is not required. Nevertheless, it is advisable to limit the
currents not higher than 400 mA.
The power supply Vmem_l must be able to sink this current
because it must be able to discharge the internal capacitance
from the level Vmem_h to the level Vmem_l. The external control
signals should be capable of driving input capacitance of about
10 pF.
Digital Signals
The digital signals control the readout of the image sensor.
These signals are:
■
■
■
■
■
■
Document Number: 38-05712 Rev. *C
Notes
4. AH: Active High
5. AL: Active Low
Sync_y (AH
synchronises the y-address register: active high. This signal is
at the same time the end of the frame or window and determines
the window width.
Clock_y (AH
this clock, the next line is selected.
Sync_x (AH
address defined by the x-address register. This pulse
synchronises the x-address register: active high. This signal is
at the same time the end of the line and determines the window
length.
Clock_x (AH
is required to achieve a pixel rate of 66MHz.
Spi_data (AH
Spi_clock (AH
data into the SPI register.
[4]
[4]
[4]
[4]
[4]
): Starts the readout of the selected line at the
[4]
): Starts the readout of the frame. This pulse
): Determines the pixel rate. A clock of 33 MHz
): Clock of the y-register. On the rising edge of
): the data for the SPI.
): clock of the SPI. This clock downloads the
Read frame I
Integration I + 1
Figure 13. Integration and Readout in Parallel
■
■
■
■
■
Test Signals
The test structures implemented in this image sensor are:
■
■
■
Timing and Readout of Image Sensor
The timing of the LUPA 4000 sensor consists of two parts. The
first part is related to the control of the pixels, the integration time,
and the signal level. The second part is related to the readout of
the image sensor. As full synchronous shutter is possible with
this image sensor, integration time and readout can be in parallel
or sequential.
In the parallel mode the integration time of the frame I is ongoing
during readout of frame I-1.
structure
Spi_load (AH
data is internally available on the rising edge of SPI_load.
Sh_kol (AL
sample and hold mode and in binning mode.
Norowsel (AH
Timing and Readout of Image
Pre_col (AL
row blanking time.
Voltage averaging (AH
averaging of 2 pixels.
Array of pixels (6*12) which outputs are tied together: used for
spectral response measurement.
Temperature diode (2): Apply a forward current of 10 μA to 100
μA and measure the voltage V
with the temperature (V
mV/°C).
End of scan pulses (do not use to trigger other signals):
❐
❐
❐
Eos_x: end of scan signal: is an output signal, indicating when
the end of the line is reached. Is not generated when doing
windowing.
Eos_y: end of scan signal: is an output signal, indicating when
the end of the frame is reached. Is not generated when doing
windowing.
Eos_spi: output signal of the SPI to check if the data is
transferred correctly through the SPI.
Read frame I + 1
Integration I + 2
[5]
[5]
): control signal of the column readout. Is used in
[4]
): Control signal of the column readout to reduce
[4]
): when the SPI register is uploaded, then the
): Control signal of the column readout. (see
[4]
T
): Signal required obtaining voltage
Figure 13
decreases with approximately 1.6
Sensor).
T
of the diode. V
CYIL1SM4000AA
shows this parallel timing
Page 13 of 31
T
varies linear
[+] Feedback