CYIL1SM4000AA-GWCES Cypress Semiconductor Corp., CYIL1SM4000AA-GWCES Datasheet - Page 19

• Manufacturer Part Number: CYIL1SM4000AA-GWCES
• Description: 4 Megapixel CMOS Image Sensor
• Manufacturer: Cypress Semiconductor Corp.

Standard Timing (200 ns)
In this case, the control signals Norowsel and pre_col are made
active for about 20 ns from the moment the next line is selected.
The time these pulses must be active is related to the biasing
resistance Pre_load. The lower this resistance, the shorter the
pulse duration of Norowsel and pre_col may be. After these
pulses are given, wait for at least 180 ns before the first pixel is
sampled. For this mode Sh_col must be made active (low) all the
time.
Backup Timing (ROT =100-200 ns)
A straightforward way of reducing the ROT is by using a sample
and hold function.
By means of Sh_col the analog data is tracked during the first
100 ns during the selection of a new set of lines. After 100 ns,
Precharging the Buses
This timing mode is exactly the same as the mode without
sample and hold, except that the prebus1 and prebus2 signals
are activated. Note that precharging of the buses can be
combined with all of the timing modes discussed earlier. The idea
Document Number: 38-05712 Rev. *C
pre_col (short pulse), Norowsel (short pulse) and Sh_col (large pulse)
Only pre_col and Norowsel control signals are required
Figure 21. Reduced Standard ROT with Sh_col Signal
Figure 20. Standard Timing for the ROT
the analog data is stored. The ROT is in this case reduced to 100
ns, but as the internal data is not stable yet, dynamic range is lost
because not the complete analog levels are reached yet after
100 ns.
Figure 21
ns-200 ns starting at the same moment as pre_col and Norowsel.
The duration of Sh_col is equal to the ROT. The shorter this time
the shorter the ROT; however, this also lowers the dynamic
range.
In case "voltage averaging" is required, the sensor must work in
this mode with Sh_col signal and a "voltage averaging" signal
must be generated after Sh_col drops and before the readout
starts (see
is to have a short pulse of about 5 ns to precharge the output
buses to a well known level. This mode makes the ghosting of
bad columns impossible.
In this mode, Nsf_load must be made much larger (at least 1
MΩ).
shows this principle. Sh_col is now a pulse of 100
Figure
17)
CYIL1SM4000AA
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