CYIL1SM4000AA-GWCES Cypress Semiconductor Corp., CYIL1SM4000AA-GWCES Datasheet - Page 7

• Manufacturer Part Number: CYIL1SM4000AA-GWCES
• Description: 4 Megapixel CMOS Image Sensor
• Manufacturer: Cypress Semiconductor Corp.

Frame Rate and Windowing
Frame Rate
To acquire a frame rate of 15 frames/sec, the output amplifier
should run at 66 MHz pixel rate or two output amplifiers should
run at 33 MHz each, assuming a Row Overhead Time (ROT) of
200 ns.
The frame period of the LUPA 4000 sensor is calculated as
follows:
Frame period = FOT + (Nr. Lines * (ROT + pixel period * Nr.
Pixels) with: FOT: Frame Overhead Time = 5 μs.
Nr. Lines: Number of Lines read out each frame (Y).
Nr. Pixels: Number of pixels read out each line (X).
ROT: ROT = 200 ns (nominal; can be further reduced).
Pixel period: 1/66 MHz = 15.15 ns.
Table 5. Frame Rate as Function of ROI Read Out and Sub Sampling
Output Amplifier
The sensor has two output amplifiers. A single amplifier can be
operated at 66 Mpixels/sec to bring the whole pixel array of 2048
by 2048 pixels at the required frame rate to the outside world.
The second output amplifier can be enabled in parallel if the
clock frequency is decreased to 33 Msamples/sec. Using only
one output-stage, the output signal is the result of multiplexing
between the two internal buses. When using two output-stages,
both outputs are in phase.
The output voltage of Out1 is between 1.3V (dark level) and 0.3V
(white level) and depends on process variations and voltage
Document Number: 38-05712 Rev. *C
2048 x 2048
1024 x 2048
1024 x 1024
640 x 480
Image Resolution (X*Y)
SPI
Frame Rate [frames f/S]
Image sensor
7bits
210
Figure 7. Output Stage Architecture.
15
31
62
DAC
Frame Readout Time [mS]
Example read out of the full resolution at nominal speed (66 MHz
pixel rate):
Frame period = 5 µs + (2048 x (200 ns + 15.15 ns x 2048)
= 64 ms ≥ 15 fps.
ROI Readout (Windowing)
Windowing is achieved by a SPI in which the starting point of the
x-address and y-address is uploaded. This downloaded starting
point initiates the shift register in the x-direction and y-direction
triggered by the Sync_x and Sync_y pulse. The minimum step
size for the x-address and the y-address is 2 (only even start
addresses can be chosen). The size of both address registers is
10-bits. For instance, when the addresses 0000000001 and
0000000001 are uploaded, the readout starts at line 2 and
column 2.
Each output-stage has two outputs. One output is the pixel
signal; the second output is a DC signal which offset can be
programmed using a 7-bit word. The DC signal is used for
common mode rejection between the two signals. The
disadvantage is an increase in power dissipation. However, this
can be reduced by setting the highest DAC voltage by means of
the SPI
supply settings. The output voltage of Out2 is determined by the
DAC.
4.7
67
32
16
Out1: Pixel signal
Out2: dc signal
Full resolution.
Subsample in X-direction.
ROI read out.
ROI read out.
CYIL1SM4000AA
Comment
Page 7 of 31
[+] Feedback