PF38F5070M0Q0B0 NUMONYX [Numonyx B.V], PF38F5070M0Q0B0 Datasheet - Page 129

• Manufacturer Part Number: PF38F5070M0Q0B0
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ StrataFlash
A.3
Note:
A.3.1
A.3.2
A.3.2.1
April 2008
309823-10
Bus Cycles and Address Capture
AADM bus operations have one or two address cycles. For two address cycles, the
upper address (A[MAX:16]) must be issued first, followed by the lower address
(A[15:0]). For bus operations with only one address cycle, only the lower address is
issued. The upper address that applies is the one that was most recently latched on a
previous bus cycle. For all read cycles, sensing begins when the lower address is
latched, regardless of whether there are one or two address cycles.
In bus cycles, the external signal that distinguishes the upper address from the lower
address is OE#. When OE# is at VIH, a lower address is captured; when OE# is at VIL,
an upper address is captured.
When the bus cycle has only one address cycle, the timing waveform is similar to A/D
MUX mode. The lower address is latched when OE# is at VIH, and data is subsequently
outputted after the falling edge of OE#.
When the device initially enters AADM mode, the upper address is internally latched as
all 0’s.
WAIT Behavior
The WAIT behavior in AADM mode functions the same as the legacy M18 non-MUX
WAIT behavior (ADMux WAIT behavior is unique). In other words, WAIT will always be
driven whenever DQ[15:0] is driven, and WAIT will tri-state whenever DQ[15:0] tri-
state. In asynchronous mode (RCR[15] = ‘1b), WAIT always indicates “valid data”
when driven. In synchronous mode (RCR[15] = ‘0b), WAIT indicates “valid data” only
after the latency count has lapsed and the data output data is truly valid.
Asynchronous Read and Write Cycles
For asynchronous read and write cycles, ADV# must be toggled high-low-high a
minimum of one time and a maximum of two times during a bus cycle. If ADV# is
toggled low twice during a bus cycle, OE# must be held low for the first ADV# rising
edge and OE# must be held high for the second ADV# rising edge. The first ADV#
rising edge (with OE# low) captures A[MAX:16]. The second ADV# rising edge (with
OE# high) captures A[15:0]. Each bus cycle must toggle ADV# high-low-high at least
one time in order to capture A[15:0]. For asynchronous reads, sensing begins when the
lower address is latched.
During asynchronous cycles, it is optional to capture A[MAX:16]. If these addresses are
not captured, then the previously captured A[MAX:16] contents will be used.
Asynchronous Read Cycles
For asynchronous read and latching specifications, refer to
Aynchronous and Latching Timings” on page
diagrams, refer to
on page 130
on page
ADV# rather than the falling edge. (i.e. TVHQV rather than TVLQV)
®
Cellular Memory (M18)
131. For AADM, note that asynchronous read access is from the rising edge of
and
Figure 62, “AADM Asynchronous Read Cycle (Latching A[15:0] only)”
Figure 61, “AADM Asynchronous Read Cycle (Latching A[MAX:0])”
130. For asynchronous read timing
Table 63, “AADM
Datasheet
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