PF38F5070M0Q0B0 NUMONYX [Numonyx B.V], PF38F5070M0Q0B0 Datasheet - Page 133

• Manufacturer Part Number: PF38F5070M0Q0B0
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ StrataFlash
A.3.3
A.3.3.1
Table 65: AADM Synchronous Timings
Notes:
1.
2.
3.
4.
5.
6.
April 2008
309823-10
Num
R201
R203
R301
R302
R303
R304
R305
R306
R307
The device must operate down to 9.6MHz in synchronous burst mode.
During the address capture phase of a read burst bus cycle, OE# timings relative to CLK shall be identical to those of
ADV# relative to CLK.
In synchronous burst read cycles, the asynchronous OE# to ADV# setup and hold times must also be met (Tghvh & Tvhgl)
to signify that the address capture phase of the bus cycle is complete.
To prevent A/D bus contention between the host and the memory device, OE# may only be asserted low after the host has
satisfied the ADDR hold spec, Tchax.
Rise and fall time specified between Vil & Vih
A read cycle may only be terminated (prior to the completion of sensing data) one time before a full bus cycle must be
allowed to complete.
t
RISE/FALL
Sym
t
t
t
t
t
t
t
t
CHQV
CHQX
AVCH
VLCH
CHAX
CHTV
ELCH
CLK
Synchronous Read and Write Cycles
Just as asynchronous bus cycles, synchronous bus cycles (RCR[15] = ‘0b) can have
one or two address cycles. If the are two address cycles, the upper address must be
latched first with OE# at VIL followed by the lower address with OE# at VIH. If there is
only one address cycle, only the lower address will be latched and the previously
latched upper address applies. For reads, sensing begins when the lower address is
latched, but for synchronous reads, addresses are latched on a rising clock CLK instead
of a rising ADV# edge.
For synchronous bus cycles with two address cycles, it is not necessary to de-assert
ADV# between the two address cycles. This allows both the upper and lower address to
be latched in only two clock periods.
Synchronous Read Cycles
For synchronous read specifications, refer to
page
•
•
•
Figure 65, “AADM Sync Burst Read Cycle (ADV# De-asserted between Address
Cycles)” on page 134
Figure 66, “AADM Sync Burst Read Cycle (ADV# Not De-asserted between Address
Cycles)” on page 134
Figure 67, “AADM Sync Burst Read Cycle (Latching A[15:0] only)” on page 135
133. For synchronous read timing diagrams, refer to the following:
®
Min (nS)
Cellular Memory (M18)
Target (104 MHz)
3.5
9
3
3
2
5
(108MHz)
Max (nS)
See note
1.5
7
7
Notes
(3)
1
5
2
4
Num
R311
R312
R313
R314
R316
R317
R318
R319
R320
Table 65, “AADM Synchronous Timings” on
Sym
t
t
t
t
t
t
t
t
t
CHVH
VHCH
CHGH
GHCH
CHVL
CHTX
CHGL
GLCH
VLVH
Min (nS)
Target (104 MHz)
2.5
2.5
t
CLK
2
2
3
2
3
3
(108MHz)
Max (nS)
2*t
CLK
Datasheet
Notes
(3)
2
4
133