LTC2488 LINER [Linear Technology], LTC2488 Datasheet - Page 12

• Manufacturer Part Number: LTC2488
• Description: 16-Bit 2-/4-Channel ?? ADC with Easy Drive Input Current Cancellation
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
LTC2488
The serial clock pin (SCK) can be confi gured as either a
master (SCK is an output generated internally) or a slave
(SCK is an input and applied externally). Master mode
(Internal SCK) is selected by simply fl oating the SCK pin.
Slave mode (External SCK) is selected by driving SCK low
during power up and each falling edge of ⎯ C ⎯ S . Specifi c
details of these SCK modes are described in the Serial
Interface Timing Modes section.
Serial Data Output (SDO)
The serial data output pin (SDO) provides the result of the
last conversion as a serial bit stream (MSB fi rst) during
the data output state. In addition, the SDO pin is used as
an end of conversion indicator during the conversion and
sleep states.
When ⎯ C ⎯ S is HIGH, the SDO driver is switched to a high
impedance state in order to share the data output line with
other devices. If ⎯ C ⎯ S is brought LOW during the conversion
phase, the ⎯ E ⎯ O ⎯ C bit (SDO pin) will be driven HIGH. Once the
conversion is complete, if ⎯ C ⎯ S is brought LOW, ⎯ E ⎯ O ⎯ C will be
driven LOW indicating the conversion is complete and the
result is ready to be shifted out of the device.
Chip Select ( ⎯ C ⎯ S )
The active low ⎯ C ⎯ S pin is used to test the conversion status,
enable I/O data transfer, initiate a new conversion, control
the duration of the sleep state, and set the SCK mode.
At the conclusion of a conversion cycle, while ⎯ C ⎯ S is HIGH,
the device remains in a low power sleep state where the
supply current is reduced several orders of magnitude. In
order to exit the sleep state and enter the data output state,
⎯ C ⎯ S must be pulled low. Data is now shifted out the SDO pin
under control of the SCK pin as described previously.
A new conversion cycle is initiated either at the conclusion
of the data output cycle (all 24 data bits read) or by pulling
⎯ C ⎯ S HIGH any time between the fi rst and 24th rising edges
of the serial clock (SCK). In this case, the data output is
aborted and a new conversion begins.
Serial Data Input (SDI)
The serial data input (SDI) is used to select the input
channel. Data is shifted into the device during the data
12
output/input state on the rising edge of SCK while ⎯ C ⎯ S is
low.
OUTPUT DATA FORMAT
The LTC2488 serial output stream is 24 bits long. The
fi rst bit indicates the conversion status, the second bit is
always zero, and the third bit conveys sign information.
The next 17 bits are the conversion result, MSB fi rst. The
remaining 4 bits are always LOW.
Bit 23 (fi rst output bit) is the end of conversion ( ⎯ E ⎯ O ⎯ C )
indicator. This bit is available on the SDO pin during the
conversion and sleep states whenever ⎯ C ⎯ S is LOW. This
bit is HIGH during the conversion cycle, goes LOW once
the conversion is complete, and is HIGH-Z when ⎯ C ⎯ S is
HIGH.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign
indicator (SIG). If the selected input (V
greater than or equal to 0V, this bit is HIGH. If V
this bit is LOW.
Bit 20 (fourth output bit) is the most signifi cant bit (MSB)
of the result. This bit in conjunction with Bit 21 also pro-
vides underrange and overrange indication. If both Bit 21
and Bit 20 are HIGH, the differential input voltage is above
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2488 Status Bits
Input Range
V
0V ≤ V
–0.5 • V
V
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB fi rst.
Bit 4 is the least signifi cant bit (LSB
Bits 3 to 0 are always LOW.
IN
IN
≥ 0.5 • V
< –0.5 • V
IN
REF
< 0.5 • V
≤ V
REF
REF
IN
REF
< 0V
Bit 23
⎯ E ⎯ O ⎯ C
0
0
0
0
Bit 22
DMY
0
0
0
0
16
).
IN
= IN
Bit 21
SIG
1
1
0
0
+
– IN
IN
Bit 20
MSB
1
0
1
0
–
< 0,
2488f
) is