LTC2488 LINER [Linear Technology], LTC2488 Datasheet - Page 17

• Manufacturer Part Number: LTC2488
• Description: 16-Bit 2-/4-Channel ?? ADC with Easy Drive Input Current Cancellation
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and ⎯ C ⎯ S to monitor and control the
state of the conversion cycle (see Figure 7).
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be fl oating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of ⎯ C ⎯ S . An internal weak pull-up resistor is active
on the SCK pin during the falling edge of ⎯ C ⎯ S ; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
The serial data output pin (SDO) is Hi-Z as long as ⎯ C ⎯ S is
HIGH. At any time during the conversion cycle, ⎯ C ⎯ S may be
pulled low in order to monitor the state of the converter.
Once ⎯ C ⎯ S is pulled LOW, SCK goes LOW and ⎯ E ⎯ O ⎯ C is output
to the SDO pin. ⎯ E ⎯ O ⎯ C = 1 while the conversion is in progress
and ⎯ E ⎯ O ⎯ C = 0 if the device is in the sleep state.
When testing ⎯ E ⎯ O ⎯ C , if the conversion is complete ( ⎯ E ⎯ O ⎯ C =
0), the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, ⎯ C ⎯ S must be
(EXTERNAL)
SDO
SCK
SDI
CS
CONVERSION
DON'T CARE
SLEEP
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15
1
EOC
1
Figure 6. External Serial Clock, 3-Wire Operation ( ⎯ C ⎯ S = 0)
“0”
0
2
0.1µF
SIG
10µF
EN
3
2.7V TO 5.5V
MSB
SGL
4
0.1V TO V
REFERENCE
ANALOG
INPUTS
VOLTAGE
ODD
5
CC
A2
6
12
13
14
10
11
8
9
7
V
REF
REF
CH0
CH1
CH2
CH3
COM
DATA INPUT/OUTPUT
CC
A1
LTC2488
7
+
–
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (F
the fi rst rising edge of SCK occurs 12µs (t
after the falling edge of ⎯ C ⎯ S . If F
oscillator of frequency f
If ⎯ C ⎯ S remains LOW longer than t
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
After the 24th rising edge of SCK a new conversion au-
tomatically begins. SDO goes HIGH ( ⎯ E ⎯ O ⎯ C = 1) and SCK
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Typically, ⎯ C ⎯ S remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing ⎯ C ⎯ S HIGH any time between the 1st rising edge and
the 24th falling edge of SCK (see Figure 8). On the ris-
ing edge of ⎯ C ⎯ S , the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
GND
SDO
A0
SCK
SDI
8
CS
F
O
5
6
2
3
1
4
9
3-WIRE
SPI INTERFACE
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
19
BIT 4
LSB
20
EOSC
DON'T CARE
BIT 3
21
, then t
BIT 2
O
22
is driven by an external
EOCTEST
EOCTEST
BIT 1
23
LTC2488
BIT 0
BIT 0
, the fi rst rising
EOCTEST
24
O
= 3.6/f
is tied LOW),
CONVERSION
= 12µs)
17
EOSC
2488 F06
2488f
.