LTC2488 LINER [Linear Technology], LTC2488 Datasheet - Page 16

• Manufacturer Part Number: LTC2488
• Description: 16-Bit 2-/4-Channel ?? ADC with Easy Drive Input Current Cancellation
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
LTC2488
state. However, the data output state may be aborted by
pulling ⎯ C ⎯ S HIGH any time between the 1st falling edge
and the 24th falling edge of SCK (see Figure 5). On the
rising edge of ⎯ C ⎯ S , the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of ⎯ C ⎯ S occurs after the 8th falling edge
of SCK, the new input channel is loaded and valid for the
next conversion cycle.
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal (see Figure 6).
⎯ C ⎯ S is permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of
16
(EXTERNAL)
SDO
SCK
SDI
CS
CONVERSION
Figure 5. External Serial Clock, Reduced Output Data Length and Valid Channel Selection
DON'T CARE
SLEEP
0.1µF
10µF
BIT 23
1
EOC
1
2.7V TO 5.5V
BIT 22
“0”
0
2
0.1V TO V
REFERENCE
ANALOG
INPUTS
VOLTAGE
BIT 21
SIG
EN
3
CC
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16
MSB
SGL
12
13
14
10
11
4
8
9
7
V
REF
REF
CH0
CH1
CH2
CH3
COM
DATA INPUT/OUTPUT
CC
ODD
LTC2488
+
–
5
the power-on reset (POR) cycle. The POR cycle typically
concludes 4ms after V
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since ⎯ C ⎯ S is tied LOW, the end-of-conversion ( ⎯ E ⎯ O ⎯ C ) can be
continuously monitored at the SDO pin during the convert
and sleep states. ⎯ E ⎯ O ⎯ C may be used as an interrupt to an
external controller. ⎯ E ⎯ O ⎯ C = 1 while the conversion is in
progress and ⎯ E ⎯ O ⎯ C = 0 once the conversion is complete.
On the falling edge of ⎯ E ⎯ O ⎯ C , the conversion result is load-
ing into an internal static shift register. The output data
can now be shifted out the SDO pin under control of the
externally applied SCK signal. Data is updated on the fall-
ing edge of SCK. The input data is shifted into the device
through the SDI pin on the rising edge of SCK. On the
24th falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as ⎯ E ⎯ O ⎯ C
for the next conversion.
GND
SCK
SDO
SDI
A2
CS
F
6
O
5
6
2
3
1
4
A1
7
4-WIRE
SPI INTERFACE
A0
8
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
BIT 15
CC
exceeds 2V. The level applied to
CONVERSION
DON'T CARE
Hi-Z
SLEEP
2488 F05
2488f