LTC2488 LINER [Linear Technology], LTC2488 Datasheet - Page 18

• Manufacturer Part Number: LTC2488
• Description: 16-Bit 2-/4-Channel ?? ADC with Easy Drive Input Current Cancellation
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
LTC2488
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of ⎯ C ⎯ S occurs after the 8th falling edge
of SCK, the new input channel is loaded and valid for the
next conversion cycle.
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion.
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal (see Figure 9). In this case, ⎯ C ⎯ S is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after V
pull-up is active during the POR cycle; therefore, the internal
serial clock timing mode is automatically selected if SCK
is fl oating or driven HIGH.
During the conversion, the SCK and the serial data output
18
(INTERNAL)
SDO
SCK
SDI
CS
CONVERSION
DON'T CARE
SLEEP
CC
<t
EOCTEST
exceeds 2V. An internal weak
BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15
1
EOC
1
Figure 7. Internal Serial Clock, Single Cycle Operation
“0”
0
2
0.1µF
10µF
SIG
EN
2.7V TO 5.5V
3
0.1V TO V
REFERENCE
MSB
ANALOG
SGL
INPUTS
VOLTAGE
4
CC
ODD
5
12
13
14
10
11
8
9
7
A2
V
REF
REF
CH0
CH1
CH2
CH3
COM
6
CC
LTC2488
+
–
A1
7
pin (SDO) are HIGH ( ⎯ E ⎯ O ⎯ C = 1). Once the conversion is
complete, SCK and SDO go LOW ( ⎯ E ⎯ O ⎯ C = 0) indicating
the conversion has fi nished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
The input data is shifted through the SDI pin on the ris-
ing edge of SCK (including the fi rst rising edge) and the
output data is shifted out the SDO pin on the falling edge
of SCK. The data input/output cycle is concluded and a
new conversion automatically begins after the 24th rising
edge of SCK. During the next conversion, SCK and SDO
remain HIGH until the conversion is complete.
The Use of a 10k Pull-Up on SCK for Internal SCK
Selection
If ⎯ C ⎯ S is pulled HIGH while the converter is driving SCK
LOW, the internal pull-up is not available to restore SCK
to a logic HIGH state if SCK is fl oating. This will cause the
device to exit the internal SCK mode on the next falling
edge of ⎯ C ⎯ S . This can be avoided by adding an external 10k
pull-up resistor to the SCK pin.
GND
SDO
SCK
SDI
DATA INPUT/OUTPUT
CS
F
O
A0
5
6
8
3
2
1
4
9
4-WIRE
SPI INTERFACE
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
V
19
CC
OPTIONAL
10k
BIT 4
LSB
20
DON'T CARE
BIT 3
21
BIT 2
22
BIT 1
23
BIT 0
24
Hi-Z
CONVERSION
2488 F07
2488f