LTC2494CUHF-PBF LINER [Linear Technology], LTC2494CUHF-PBF Datasheet - Page 16

• Manufacturer Part Number: LTC2494CUHF-PBF
• Description: 16-Bit 8-/16-Channel ?? ADC with PGA and Easy Drive Input Current Cancellation
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
LTC2494
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign
indicator (SIG). If the selected input (V
greater than or equal to 0V, this bit is HIGH. If V
this bit is LOW.
Bit 20 (fourth output bit) is the most signifi cant bit (MSB)
of the result. This bit in conjunction with Bit 21 also pro-
vides underrange and overrange indication. If both Bit 21
and Bit 20 are HIGH, the differential input voltage is above
+FS. If both Bit 21 and Bit 20 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2494 Status Bits
Input Range
V
0V ≤ V
–0.5 • V
V
Bits 20 to 4 are the 16-bit plus sign conversion result
MSB fi rst.
Bit 4 is the least signifi cant bit (LSB
Bits 3 to 0 are always LOW.
(EXTERNAL)
16
IN
IN
≥ 0.5 • V
< –0.5 • V
SDO
SCK
SDI
IN
CS
REF
< 0.5 • V
CONVERSION
/Gain ≤ V
DON'T CARE
REF
REF
Hi-Z
/Gain
/Gain
REF
IN
/Gain
< 0V
SLEEP
Figure 3. Channel Selection, Confi guration Selection and Data Output Timing
Bit 23
BIT 23
EOC
1
EOC
1
0
0
0
0
BIT 22
“0”
0
2
Bit 22
DMY
BIT 21
0
0
0
0
16
SIG
EN
3
).
IN
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
MSB
SGL
= IN
4
Bit 21
SIG
1
1
0
0
ODD
+
5
– IN
IN
Bit 20
A2
MSB
6
1
0
1
0
–
< 0,
) is
DATA INPUT/OUTPUT
A1
7
A0
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device, CS
must fi rst be driven LOW. EOC is seen at the SDO pin of
the device once CS is pulled LOW. `E`O`C changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the fi rst
rising edge of SCK. Bit 22 is shifted out of the device on
the fi rst falling edge of SCK. The fi nal data bit (Bit 0) is
shifted out on the on the falling edge of the 23rd SCK and
may be latched on the rising edge of the 24th SCK pulse.
On the falling edge of the 24th SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 23) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the IN
between –0.3V and V
erating range) a conversion result is generated for any
differential input voltage V
to +FS = 0.5 • V
greater than +FS, the conversion result is clamped to the
value corresponding to +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value –FS – 1LSB.
8
EN2
9
IM
10
FA
11
REF
FB
12
/Gain. For differential input voltages
CC
SPD
13
+ 0.3V (absolute maximum op-
IN
BIT 10
GS2
14
from –FS = –0.5 • V
BIT 9
GS1
15
+
and IN
GS0
16
–
BIT 0
pins remains
24
DON'T CARE
REF
CONVERSION
Hi-Z
/Gain
2494fb
2494 F03