LTC2494CUHF-PBF LINER [Linear Technology], LTC2494CUHF-PBF Datasheet - Page 22

• Manufacturer Part Number: LTC2494CUHF-PBF
• Description: 16-Bit 8-/16-Channel ?? ADC with PGA and Easy Drive Input Current Cancellation
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
LTC2494
(EXTERNAL)
Typically, CS remains LOW during the data output/input
state. However, the data output state may be aborted by
pulling CS HIGH any time between the 1st falling edge
and the 24th falling edge of SCK (see Figure 7). On the
rising edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCK, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCK, the new channel
is still loaded, but the converter confi guration remains
unchanged. In order to program both the input channel
and converter confi guration, CS must go high after the
16th falling edge of SCK (at this point all data has been
shifted into the device).
22
SDO
SCK
SDI
CS
CONVERSION
DON'T CARE
SLEEP
Hi-Z
BIT 23
1
EOC
1
BIT 22
“0”
Figure 6. External Serial Clock, Single Cycle Operation
0
2
10μF
2.7V TO 5.5V
BIT 21
SIG
EN
3
0.1V TO V
0.1μF
REFERENCE
ANALOG
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13
INPUTS
VOLTAGE
MSB
SGL
4
CC
ODD
5
•
•
•
•
•
•
28
29
30
15
16
23
8
7
V
REF
REF
CH0
CH7
CH8
CH15
COM
A2
CC
•
•
•
•
•
•
6
LTC2494
+
–
A1
7
GND
SDO
SCK
SDI
CS
F
DATA INPUT/OUTPUT
O
External Serial Clock, 3-Wire I/O
This timing mode uses a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal (see Figure 8).
CS is permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is typically
concluded 4ms after V
SCK at this time determines if SCK is internally generated
or externally applied. In order to enter the external SCK
mode, SCK must be driven LOW prior to the end of the
POR cycle.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller. EOC = 1 while the conversion is in
progress and EOC = 0 once the conversion is complete.
1,3,4,5,6,31,32,33,39
A0
38
35
34
37
36
8
EN2
9
4-WIRE
SPI INTERFACE
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
IM
10
FA
11
BIT 12 BIT 11
FB
12
CC
SPD
13
exceeds 2V. The level applied to
BIT 10
GS2
14
BIT 9
GS1
15
GS0
16
BIT 0
DON'T CARE
24
CONVERSION
2494 F06
Hi-Z
2494fb