LTC2494CUHF-PBF LINER [Linear Technology], LTC2494CUHF-PBF Datasheet - Page 24

• Manufacturer Part Number: LTC2494CUHF-PBF
• Description: 16-Bit 8-/16-Channel ?? ADC with PGA and Easy Drive Input Current Cancellation
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
LTC2494
On the falling edge of EOC, the conversion result is load-
ing into an internal static shift register. The output data
can now be shifted out the SDO pin under control of the
externally applied SCK signal. Data is updated on the fall-
ing edge of SCK. The input data is shifted into the device
through the SDI pin on the rising edge of SCK. On the
24th falling edge of SCK, SDO goes HIGH, indicating a
new conversion has begun. This data now serves as EOC
for the next conversion.
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 9).
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be fl oating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
24
(INTERNAL)
SDO
SCK
SDI
CS
CONVERSION
DON'T CARE
SLEEP
<t
EOCTEST
BIT 23
1
EOC
1
BIT 22
“0”
Figure 9. Internal Serial Clock, Single Cycle Operation
0
2
10μF
BIT 21
2.7V TO 5.5V
SIG
EN
3
0.1V TO V
0.1μF
REFERENCE
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13
MSB
ANALOG
SGL
INPUTS
VOLTAGE
4
CC
ODD
5
•
•
•
•
•
•
28
29
30
15
16
23
8
7
A2
V
REF
REF
CH0
CH7
CH8
CH15
COM
6
CC
•
•
•
•
•
•
LTC2494
+
–
A1
7
SDO
GND
SCK
SDI
DATA INPUT/OUTPUT
CS
F
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and `E`O`C is
output to the SDO pin. EOC= 1 while the conversion is in
progress and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC =
0), the device will exit sleep state. In order to return to the
sleep state and reduce the power consumption, CS must be
pulled HIGH before the device pulls SCK HIGH. When the
device is using its own internal oscillator (F
the fi rst rising edge of SCK occurs 12μs (t
after the falling edge of CS. If F
oscillator of frequency f
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
O
A0
1,3,4,5,6,31,32,33,39
8
34
38
35
37
36
EN2
9
4-WIRE
SPI INTERFACE
IM
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
10
FA
11
V
BIT 12 BIT 11
CC
FB
12
OPTIONAL
10k
EOSC
SPD
13
, then t
BIT 10
GS2
14
O
is driven by an external
BIT 9
GS1
EOCTEST
15
EOCTEST
GS0
16
, the fi rst rising
EOCTEST
O
= 3.6/f
BIT 0
is tied LOW),
24
DON'T CARE
= 12μs)
Hi-Z
CONVERSION
EOSC
2494fb
2494 F09
.