LTC2494CUHF-PBF LINER [Linear Technology], LTC2494CUHF-PBF Datasheet - Page 25

• Manufacturer Part Number: LTC2494CUHF-PBF
• Description: 16-Bit 8-/16-Channel ?? ADC with PGA and Easy Drive Input Current Cancellation
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
After the 24th rising edge of SCK a new conversion au-
tomatically begins. SDO goes HIGH (EOC = 1) and SCK
remains HIGH for the duration of the conversion cycle.
Once the conversion is complete, the cycle repeats.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH any time between the 1st rising edge and
the 24th falling edge of SCK (see Figure 10). On the ris-
ing edge of CS, the device aborts the data output state
and immediately initiates a new conversion. In order to
program a new input channel, 8 SCK clock pulses are
required. If the data output sequence is aborted prior to
the 8th falling edge of SCK, the new input data is ignored
and the previously selected input channel remains valid.
If the rising edge of CS occurs after the 8th falling edge of
SCK, the new input channel is loaded and valid for the next
conversion cycle. If CS goes high between the 8th falling
edge and the 16th falling edge of SCK, the new channel
is still loaded, but the converter confi guration remains
(INTERNAL)
SDO
SCK
SDI
CS
CONVERSION
Figure 10. Internal Serial Clock, Reduced Data Output Length with Valid Channel and Confi guration Selection
DON'T CARE
SLEEP
<t
EOCTEST
BIT 23
1
EOC
1
BIT 22
“0”
0
2
BIT 21
SIG
EN
3
10μF
2.7V TO 5.5V
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13
MSB
SGL
4
0.1V TO V
0.1μF
REFERENCE
ANALOG
INPUTS
VOLTAGE
ODD
5
CC
A2
6
•
•
•
•
•
•
28
29
30
15
16
23
8
7
V
REF
REF
CH0
CH7
CH8
CH15
COM
A1
CC
•
•
•
•
•
•
7
LTC2494
+
–
DATA INPUT/OUTPUT
unchanged. In order to program both the input channel
and converter confi guration, CS must go high after the
16th falling edge of SCK (at this point all data has been
shifted into the device).
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion.
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal (see Figure 11). In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after V
pull-up is active during the POR cycle; therefore, the internal
serial clock timing mode is automatically selected if SCK
is fl oating or driven HIGH.
A0
SDO
GND
8
SCK
SDI
CS
F
O
1,3,4,5,6,31,32,33,39
EN2
38
35
34
37
36
9
IM
10
4-WIRE
SPI INTERFACE
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
FA
11
BIT 12 BIT 11
FB
12
V
CC
SPD
OPTIONAL
10k
CC
13
BIT 10
exceeds 2V. An internal weak
GS2
14
BIT 9
GS1
15
BIT 8
GS0
LTC2494
16
BIT 7
DON'T CARE
25
CONVERSION
Hi-Z
2494fb
2494 F10