LTC2494CUHF-PBF LINER [Linear Technology], LTC2494CUHF-PBF Datasheet - Page 21

• Manufacturer Part Number: LTC2494CUHF-PBF
• Description: 16-Bit 8-/16-Channel ?? ADC with PGA and Easy Drive Input Current Cancellation
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
External Serial Clock, Single Cycle Operation
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 6).
The external serial clock mode is selected during the power-
up sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
Figure 4. Internal PTAT Digital Output vs Temperature
1020
960
800
640
480
320
160
0
0
V
V
SLOPE = 2.45 LSB
CC
REF
= 5V
= 5V
100
TEMPERATURE (K)
Table 6. LTC2494 Interface Timing Modes
CONFIGURATION
External SCK, Single Cycle
Conversion
External SCK, 3-Wire I/O
Internal SCK, Single Cycle
Conversion
Internal SCK, 3-Wire I/O,
Continuous Conversion
16
/K
200
300
2494 F04
400
SOURCE
External
External
Internal
Internal
SCK
CYCLE CONTROL
CONVERSION
CS and SCK
Continuous
CS↓
SCK
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device remains
in the sleep state until the fi rst rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDI pin on each rising edge of SCK (including the fi rst rising
edge). The channel selection and converter confi guration
mode will be used for the following conversion cycle. If
the input channel or converter confi guration is changed
during this I/O cycle, the new settings take effect on the
conversion cycle following the data input/output cycle.
The output data is shifted out the SDO pin on each falling
edge of SCK. This enables external circuitry to latch the
output on the rising edge of SCK. EOC can be latched on
the fi rst rising edge of SCK and the last bit of the conver-
sion result can be latched on the 24th rising edge of SCK.
On the 24th falling edge of SCK, the device begins a new
conversion and SDO goes HIGH (EOC = 1) indicating a
conversion is in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
DATA OUTPUT
CS and SCK
CONTROL
Internal
–1
–2
–3
–4
–5
SCK
CS↓
5
4
3
2
1
0
Figure 5. Absolute Temperature Error
–55
–30
CONNECTION AND
–5
TEMPERATURE (°C)
WAVEFORMS
Figures 9, 10
Figures 6, 7
Figure 11
Figure 8
20
45
70
95
LTC2494
2494 F05
120
21
2494fb