PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 113

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

In SPP Compatible mode, the parallel port does not write
data to the output signals. Bit 5 of the CTR register has no
effect in this state. If data is written (WR goes low), the data
is sent to the output signals PD7-0. If a read cycle is initiated
(RD goes low), the system reads the contents of the output
latch, and not data from the PD7-0 output signals.
In SPP Extended mode, the parallel port can read and write
external data via PD7-0. In this mode, bit 5 sets the direction
for data in or data out, while read or write cycles are possi-
ble in both settings of bit 5.
If bit 5 of CTR is cleared to 0, data is written to the output
signals PD7-0 when a write cycle occurs. (if a read cycle oc-
curs in this setting, the system reads the output latch, not
data from PD7-0).
If bit 5 of CTR is set to 1, data is read from the output signals
PD7-0 when a read cycle occurs. A write cycle in this setting
only writes to the output latch, not to the output signals PD7-
0.
The reset value of this register is 0.
Extended
0
7
Mode
FIGURE 6-1. DTR Register Bitmap (SPP Mode)
SPP
D7
0
6
D6
0
5
D5
0
Bit 5 of
4
CTR
D4
0
1
0
1
0
3
D3
0
2
Data Bits
RD WR
D2
1
1
0
0
0
1
D1
0
0
0
0
1
1
D0
Reset
Required
Data read from PD7-0.
Data written to PD7-0.
Data written is latched
Data read from output
SPP Data Register
Result
latch.
Parallel Port (Logical Device 4)
Offset 00h
(DTR)
113
6.2.3
This read-only register holds status information. A system
write operation to STR is an invalid operation that has no ef-
fect on the parallel port.
Bit 0 - Time-Out Status
Bit 1 - Reserved
Bit 2 - IRQ Status
Bit 3 - ERR Status
Bit 4 - SLCT Status
1
7
In EPP modes only, this is the time-out status bit. In all
other modes this bit has no function and has the con-
stant value 1.
This bit is cleared when an EPP mode is enabled.
Thereafter, this bit is set to 1 when a time-out occurs in
an EPP cycle and is cleared when STR is read.
In EPP modes:
0 - An EPP mode is set. No time-out occurred since
1 - Time-out occurred on EPP cycle (minimum of 10
This bit is reserved and is always 1.
In all modes except SPP Extended, this bit is always 1.
In SPP Extended mode this bit is the IRQ status bit. It re-
mains high unless the interrupt request is enabled (bit 4 of
CTR set high). This bit is high except when latched low
when the ACK signal makes a low to high transition, indi-
cating a character is now being transferred to the printer.
Reading this bit resets it to 1.
0 - Interrupt requested in SPP Extended mode.
1 - No interrupt requested. (Default)
This bit reflects the current state of the printer error sig-
nal, ERR. The printer sets this bit low when there is a
printer error.
0 - Printer error.
1 - No printer error.
This bit reflects the current state of the printer select sig-
nal, SLCT. The printer sets this bit high when it is on-line
and selected.
0 - No printer selected.
1 - Printer selected and online.
FIGURE 6-2. STR Register Bitmap (SPP Mode)
Printer Status
1
6
STR was last read.
Status Register (STR), Offset 01h
sec). (Default)
ACK Status
1
5
PE Status
1
4
SLCT Status
1
3
ERR Status
1
2
IRQ Status
1
1
Reserved
1
0
Reset
Required
Time-Out Status
SPP Status Register
www.national.com
Offset 01h
(STR)