PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 147

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

7.11.6 Bank Selection Register (BSR), All Banks,
The Bank Selection Register (BSR) selects which register
bank is to be accessed next.
About accessing this register see the description of bit 7 of
the LCR Register.
Bits 6-0 - Bank Selection
Bit 7 - Bank Selection Enable (BKSE)
7
0
1
1
1
1
1
1
1
1
1
1
1
0
7
When bit 7 is set to 1, bits 6-0 of BSR select the bank,
as shown in Table 7-9.
0 - Bank 0 is selected.
1 - Bits 6-0 specify the selected bank.
0
6
0
1
1
1
1
1
1
1
1
1
1
6
x
BKSE-Bank Selection Enable
Offset 03h
TABLE 7-9. Bank Selection Encoding
0
5
FIGURE 7-12. BSR Register Bitmap
5
1
1
1
1
1
1
1
0
x
x
x
x
BSR Bits
0
4
4
x
x
x
x
0
0
0
0
1
1
1
x
0
3
3
x
x
x
x
0
0
1
1
0
0
1
x
0
2
2
x
x
x
x
0
1
0
1
0
1
x
x
Bank Selection
0
1
1
x
x
1
x
0
0
0
0
0
0
0
0
0
0
0
x
x
x
1
0
0
0
0
0
0
0
0
Reset
Required
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
Reserved
Reserved
Selected
Bank
0
1
1
1
2
3
4
5
6
7
Bank Selection
Register (BSR)
LCR is writ-
LCR is not
Offset 03h
All Banks,
written
LCR
ten
147
7.11.7 Modem/Mode Control Register (MCR), Bank 0,
This register controls the interface with the modem or data
communications set, and the device operational mode
when the device is in the Extended mode. The register
function differs for Extended and Non-Extended modes.
Modem/Mode Control Register (MCR), Non-Extended
Mode, Bank 0, Offset 04h
Bit 0 - Data Terminal Ready (DTR)
Bit 1 - Request To Send (RTS)
Bit 2 - Loopback Interrupt Request (RILP)
Bit 3 - Interrupt Signal Enable (ISEN) or Loopback DCD
(DCDLP)
Bit 4 - Loopback Enable (LOOP)
Bits 7-5 - Reserved
FIGURE 7-13. MCR Register Bitmap, Non-Extended
0
0
7
This bit controls the DTR signal output. When set to 1,
DTR is driven low. When loopback is enabled (LOOP is
set to 1), this bit internally drives DSR.
This bit controls the RTS signal output. When set to 1,
drives RTS low. When loopback is enabled (LOOP is
set), this bit drives CTS, internally.
When loopback is enabled, this bit internally drives RI.
Otherwise it is unused.
In normal operation (standard 16450 or 16550) mode,
this bit controls the interrupt signal and must be set to 1
in order to enable the interrupt request signal.
When loopback is enabled, the interrupt output signal is
always enabled, and this bit internally drives DCD.
New programs should always keep this bit set to 1 dur-
ing normal operation. The interrupt signal should be
controlled through the Plug-n-Play logic.
When this bit is set to 1, it enables loopback. This bit ac-
cesses the same internal register as bit 4 of the EXCR1
register. (see “Bit 4 - Loopback Enable (LOOP)” on page
154 for more information on the Loopback mode).
0 - Loopback disabled. (Default)
1 - Loopback enabled.
Read/Write 0.
0
0
Reserved
6
Offset 04h
Reserved
0
0
5
0
Reserved
4
Non-Extended UART mode
0
3
LOOP
0
2
ISEN or DCDLP
0
1
RILP
Mode
RTS
0
0
Reset
Required
DTR
Modem Control
Register (MCR)
www.national.com
Offset 04h
Bank 0,