PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 143

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Bit 5 - Transmitter Empty Interrupt Enable (TXEMP_IE)
Bits 7,6 - Reserved
Interrupt Enable Register (IER), Consumer-IR Mode,
Bank 0, Offset 01h
Figure 7-7 shows the bitmap of the Interrupt Enable Regis-
ter (IER) in this mode.
FIGURE 7-7. IER Register Bitmap, Consumer-IR Mode
Bit 1-0 -
Bit 2 - Link Status Interrupt Enable (LS_IE) or TX_FIFO
Underrun Interrupt Enable (TXUR_IE)
Bit 7-3 -
0
7
Setting this bit enables interrupt generation if the trans-
mitter and TX_FIFO become empty.
0 - Disable Transmitter Empty interrupts (Default)
1 - Enable Transmitter Empty interrupts.
Reserved.
Same as in the Extended Modes of UART and Sharp-IR
(See previous sections).
On reception, Setting this bit enables Link Status Inter-
rupts.
On transmission, Setting this bit enables TX_FIFO un-
derrun interrupts.
0 - Disable Link Status and TX_FIFO underrun inter-
1 - Enable Link Status and TX_FIFO underrun interrupts.
Same as in the Extended Modes of UART and Sharp-IR
(See the section “Interrupt Enable Register (IER), in the
Extended Modes of UART, Sharp-IR and SIR” on page
142).
Reserved
0
6
rupts (Default)
Reserved
0
5
Consumer-IR Mode
TXEMP_IE
0
4
DMA_IE
0
3
MS_IE
0
2
LS_IE or TXUR_IE
0
1
0
TXLDL_IE
0
Reset
Required
RXHDL_IE
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
Interrupt Enable
Register (IER)
Offset 01h
Bank 0,
143
7.11.3 Event Identification Register (EIR),
The Event Identification Register (EIR) and the FIFO Con-
trol Register (FCR) (see next register description) share the
same address. The EIR is accessed during CPU read cycles
while the FCR is accessed during CPU write cycles.The
Event Identification Register (EIR) indicates the interrupt
source. The function of this register changes according to the
selected mode of operation.
Event Identification Register (EIR), Non-Extended Mode
When Extended mode is not selected (EXT_SL bit in
EXCR1 register is set to 0), this register is the same as in
the 16550.
In a Non-Extended UART mode, this module prioritizes in-
terrupts into four levels. The EIR indicates the highest level
of interrupt that is pending. The encoding of these interrupts
is shown in Table 7-3.
When the EIR is being read, the display of the highest pri-
ority pending interrupt is frozen; new interrupt requests are
recorded, but the indication is not updated until the access
is complete.
Bit 0 - Interrupt Pending Flag (IPF)
Bits 2,1 - Interrupt Priority 1,0 (IPR1,0)
Bit 3 - RX_FIFO Time-Out (RXFT)
Bits 5,4 - Reserved
Bit 7,6 - FIFOs Enabled (FEN1,0)
FIGURE 7-8. EIR Register Bitmap, Non-Extended Modes
0
7
0 - There is an interrupt pending.
1 - No interrupt pending. (Default)
When bit 0 (IPF) is 0, these bits indicate the pending in-
terrupt with the highest priority. See Table 7-3.
Default value is 00.
In the 16450 mode, this bit is always 0. In the 16550
mode (FIFOs enabled), this bit is set to 1 when an
RX_FIFO read time-out occurred and the associated in-
terrupt is currently the highest priority pending interrupt.
Read/Write 0.
0 - No FIFO enabled. (Default)
1 - FIFOs are enabled (bit 0 of FCR is set to 1).
0
FEN1 - FIFOs Enabled
6
Bank 0, Offset 02h
0
0
5
Non-Extended Modes, Read Cycles
FEN0 - FIFOs Enabled
0
0
4
Reserved
0
Reserved
3
RXFT - RX_FIFO Time-Out
0
2
0
IPR1 - Interrupt Priority 1
1
IPR0 - Interrupt Priority 0
1
0
Reset
Required
IPF - Interrupt Pending
Event Identification
Register (EIR)
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Offset 02h
Bank 0,