PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 176

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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Upon reset and upon activation of the power management
device, all trigger events are disabled, i.e., bits are cleared
to zero.
See “The WATCHDOG Feature” on page 172 for more in-
formation.
Bit 0 - KBC IRQ Trigger Enable
Bit 1 - Mouse IRQ Trigger Enable
Bit 2 - UART1 IRQ Trigger Enable
Bit 3 - UART2 IRQ Trigger Enable
Bits 7-4 - Reserved
0
7
This bit enables the IRQ assigned to the KBC to trigger
reloading of the WATCHDOG timer.
Reset clears this bit to 0.
0 - KBC IRQ trigger disabled. (Default)
1 - An active KBC IRQ signal triggers reloading of the
This bit enables the IRQ assigned to the mouse to trig-
ger reloading of the WATCHDOG timer.
Reset clears this bit to 0.
0 - Mouse IRQ trigger disabled. (Default)
1 - An active mouse IRQ signal triggers reloading of
This bit enables the IRQ assigned to UART1 to trigger
reloading of the WATCHDOG timer.
Reset clears this bit to 0.
0 - UART1 IRQ trigger disabled. (Default)
1 - An active UART1 IRQ signal triggers reloading of
This bit enables the IRQ assigned to UART2 to trigger
reloading of the WATCHDOG timer.
Reset clears this bit to 0.
0 - UART2 IRQ trigger disabled. (Default)
1 - An active UART2 IRQ signal triggers reloading of
Reserved
0
6
WATCHDOG timer.
the WATCHDOG timer.
the WATCHDOG timer.
the WATCHDOG timer.
FIGURE 9-9. WDCF Register Bitmap
0
5
Reserved
0
4
0
3
UART2 IRQ Trigger Enable
0
2
UART1 IRQ Trigger Enable
0
1
Mouse IRQ Trigger Enable
0
WATCHDOG Configuration
0
Reset
Required
KBC IRQ Trigger Enable
Register (WDCF)
Power Management (Logical Device 8)
Index 06h
176
9.2.10 WATCHDOG Status Register (WDST),
Bit 1 of this register contains the value of the WDO signal,
for monitoring by software.
On reset or on PM logical device activation this register is
initialized to 01h.
See “The WATCHDOG Feature” on page 172 for more in-
formation.
Bit 0 - WDO Value
Bits 7-1 - Reserved
0
7
This read-only bit reflects the value of WDO. It is initial-
ized to 1 by a hardware reset.
This bit reflects the status of the WDO signal, even if
WDO is not configured for output by bit 6 of SuperI/O
Configuration register 2, in which case the pin is used
for GPIO17.
0 - WDO is active.
1 - WDO is not active. (Default)
These bits are reserved.
0
6
Index 07h
FIGURE 9-10. WDST Register Bitmap
0
5
0
4
0
3
Reserved
0
2
0
1
1
0
Reset
Required
WDO Value
WATCHDOG Status
Register (WDST)
Index 07h