SAA7205 Philips Semiconductors, SAA7205 Datasheet - Page 12

• Manufacturer Part Number: SAA7205
• Description: MPEG-2 systems demultiplexer
• Manufacturer: Philips Semiconductors

Philips Semiconductors
It should be noted that audio and video data can be
optionally combined on the output bus to interface to
combined audio/video decoders. In this mode the video
bus is controlled by the VSEL signal, an audio request
signal (AUDATR) and a video request signal (VREQ;
optional). Video and audio bytes are output at 9 MBytes
and are interleaved with a programmable audio/video
ratio.
7.1.8
The PCR processor is capable of regenerating a local
system time clock. This block contains a digital clock
recovery loop. Two local clock counters generate an
absolute timing value (cycle time approximately 24 hours),
which is used to verify the phase relationship between the
local system time clock and the transmitter reference clock
(Program Clock Reference, or PCR). Two STC counters
are implemented to allow for correct handling of PCR
discontinuations.
7.1.9
These two PTS/DTS processors are capable of
synchronizing attached source decoders. The PTS/DTS
processors retrieve time stamps from the incoming
transport stream. They also compare emulated time
stamps (PTS/DTS) with the local absolute time value
generated by the PCR processor. In the event of equality
a microcontroller interrupt is generated.
The microcontroller can respond to this pulse by
instructing the attached source decoders to start decoding,
or to start presentation. For audio, the PTS values are
stored in the audio FIFO to be used for synchronization of
the FIFO output stream (called lip-sync).
7.1.10
There are two FIFO buffers for audio and video (6 kBytes
and 768 Bytes respectively), including buffer control, to
interface between different clock systems. These FIFOs
are filled at byte clock (CCLKI/3) frequency and emptied
on the acquisition clocks of the respective source
decoders [9 MByte/s for video and combined audio/video,
Table 1 Filter types
1997 Jan 21
Short (sections)
Long (sections)
Subtitling
MPEG-2 systems demultiplexer
FILTER TYPE
P
T
FIFO
IME STAMP PROCESSORS
ROGRAM CLOCK REFERENCE PROCESSOR
BUFFERS
NUMBER OF FILTERS
12
4
1
BUFFER SIZE
12
4
1
12
4 kByte
4 kByte
1 kByte
and a frequency in the range 32 to 448 kbit/s (hardware
sync), or 9 Mbit/s (software sync) for audio].
7.1.11
The microcontroller interface provides protocol handling
for the memory mapped I/O control bus (Philips
P90CE201 compatible). This module also contains an
interrupt request handler and data filters for retrieval of
Program Specific Information (PSI), service information
(SI), Electronic Program Guides (EPG) (private sections),
subtitling (private sections) and low speed (LS) data
(private).
7.1.11.1
The short filters select data on the basis of PIDs and a
combination of MPEG-2 section addressing fields.
Selected data is stored in twelve 1 kByte (constrained
random access) buffers. These buffers are located in the
external SRAM memory and can be read by the
microcontroller. The short filters are capable of monitoring
12 section streams simultaneously.
7.1.11.2
The long filters also select data on the basis of PIDs and a
combination of MPEG-2 section addressing fields.
Selected data is stored in four 4 kByte (constrained
random access) buffers. These buffers are located in the
external SRAM memory and can be read by the
microcontroller. The long filters are capable of monitoring
4 section streams simultaneously.
7.1.11.3
The subtitling filter is capable of retrieving transport packet
payloads or PES payloads from the input stream, on the
basis of a programmable filter. It is also capable of
retrieving adaptation field and PES header private data.
Data is stored in a 4 kByte FIFO which is located in the
external SRAM memory and can be read by the
microcontroller.
M
ICROCONTROLLER INTERFACE
Short filters
Long filters
Subtitling filter
PES and PES payload (ES), adaption field
private data, PES header private data
REMARKS
Preliminary specification
SAA7205H