SAA7205 Philips Semiconductors, SAA7205 Datasheet - Page 39

• Manufacturer Part Number: SAA7205
• Description: MPEG-2 systems demultiplexer
• Manufacturer: Philips Semiconductors

Philips Semiconductors
A typical example of communication between
microcontroller and demultiplexer is illustrated in Fig.25.
The demultiplexer contains an auto-increment address
counter which can be loaded by performing a write
address operation. The subsequent operation, whether
read or write, is then performed at that address.
1997 Jan 21
IRQ: an active LOW interrupt request signal.
An interrupt is set should if one of the 14 bits in the
demultiplexer internal interrupt register is set.
The interrupt mechanism consists of 3
1
The interrupt status registers enable the microcontroller
to monitor the momentary status of the interrupts. This
is particularly useful during read actions in the
demultiplexer’s section buffers, since the status bit in
question (interrupt: ‘flt [F to 0]_stat’, address 0x0003,
see Table 13) is reset as soon as the buffer is empty.
The interrupt mask register (address 0x0001,
see Table 13) allows individual interrupts to be
prevented from resetting IRQ (to 0). Prior to latching the
interrupts status bits into the interrupt register, they are
logically ANDed with the mask. The interrupt register is
reset (to 0000000000000000) as soon as it is
addressed (0x0000) by the microcontroller.
MPEG-2 systems demultiplexer
The interrupt register is reset upon addressing.
See Table 8 for definition of interrupt mechanism.
16-bit register in total, as indicated in Fig.24.
Fig.24 Demultiplexer microcontroller interrupt mechanism.
handbook, halfpage
0x0002/0x0003
14-bit interrupt
30-bit status
14-bit mask
(read/write)
(read only)
(write only)
14-bit and
0x0001
0x0000
IRQ
MGG768
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enables/disables
individual interrupts
latched interrupts, indicating
which interrupt(s) set IRQ
The operation after that is then automatically performed at
address + 1, unless a new address is loaded.
Note: avoid resetting the auto-increment address counter
to 0x0000, when not handling interrupts, as addressing it
causes the interrupt register to be reset. Interrupt
information might consequently be lost.
The demultiplexer internal register and buffer addresses
are organized as indicated in Fig.26. The first 4 address
(15 to 12) bits are used to select either control registers (0)
or the data buffers (range 1 to 3, 8 to F). In the data buffer
mode, the remaining address bits (11 to 0) are part of the
word address (range depending on the data buffer). In the
register mode, bits 11 to 8 specify the register unit
number. The remaining 8 bits of the address (7 to 0)
specify register addresses within a selected unit. The
address range in a specific register unit depends on the
number of registers present and is different for each unit.
For details refer to see Table 13.
momentary status of the
individual interrupt bits
Preliminary specification
SAA7205H