SAA7205 Philips Semiconductors, SAA7205 Datasheet - Page 26

• Manufacturer Part Number: SAA7205
• Description: MPEG-2 systems demultiplexer
• Manufacturer: Philips Semiconductors

Philips Semiconductors
The FIFO output process can operate in stand alone, but
it can also be controlled by the microcontroller. During
start-up the read address counter is reset to 0. After the
FIFO input process is started the first PTS is retrieved from
the first three byte positions in the FIFO. To this PTS value
a programmable offset is applied [resulting in: PTS* = PTS
- ‘audio_pts_offset’, addresses 0x060D to 0x060E (two’s
complement), see Table 13] to compensate for the delay
of the audio decoder. The FIFO output process is
subsequently put on hold as long as the System Time
Clock (STC) counter has not reached the value of PTS*.
When the STC counter exceeds the PTS* position the
output process is started and audio data is retrieved from
the FIFO at a speed indicated by the bit rate parameter in
the frame header (32 to 448 kbit/s).Only valid audio data is
passed to the output. Each time a valid PTS occurs at the
FIFO output the difference between PTS* and STC is
calculated and stored, to enable reading by the
microcontroller (words: ‘audio_stc_min_epts’, addresses
0x060F to 0x0611, see Table 13). Two modes of
operation can be selected by the microcontroller (bit
‘ c_free_run’, address 0x060A, see Table 13):
After the input process is started a continuous check is
performed on the distance between the FIFO read and
write counters. If one pointer approaches the other one a
wrap around may take place (buffer underflow or
overflow), causing synchronization to be lost completely.
Should this occur an internal start-up (restart) is initiated
automatically and signalled to the microcontroller
(interrupt: ‘irpt_audio_restart’, address 0x0000,
see Table 13).
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PTS controlled: (‘ c_free_run’ = 0) the output process is
put on hold if PTS* is greater than the STC counter
position. Otherwise the output process continues at the
given bit-rate. In this mode, the output process could be
halted for every valid PTS which is being output by the
FIFO.
Free running: (uc_free_run = 1) the output process is
synchronized once during start-up only and continues at
the derived bit rate without resynchronizing to new PTS
time stamps. The difference between PTS* and the STC
value is sampled and stored at the moment a PTS is
taken from the FIFO (words: ‘audio_stc_min_epts’,
addresses 0x060F to 0x0611, see Table 13). This event
is signalled to the microcontroller (interrupt:
‘irpt_audio_diff’, address 0x0000, see Table 13).
A decision for a restart (bit ‘ c_frc_restart’, address
0x060A, see Table 13) can consequently be taken in
software, whenever the difference ‘audio_stc_min_epts’
exceeds a certain audible threshold (20 ms for
instance).
MPEG-2 systems demultiplexer
26
If a third party audio decoder is capable of adjusting the
output delay by itself, the demultiplexer audio output
process does not have to be PTS controlled. In this case
the functionality of the demultiplexer audio interface can
optionally be reduced to (bit ‘ c_sw_sync’ = 1, address
0x060A, see Table 13):
In this so called software sync mode (‘ c_sw_sync’ = 1)
the FIFO input runs freely. Either entire PES packets (bit
‘audio_pes’ = 1, address 0x060A, see Table 13), or the
payload of selected PES packets is stored in the FIFO at
subsequent addresses starting from 0 at start-up.
PTS information is stored in the FIFO but is also available
in registers to make it accessible for the microcontroller
(words: ‘audio_pts’, addresses 0x0601 to 0x0602,
see Table 13).
In the software sync mode, the FIFO output process is
controlled by the microcontroller. The read address
counter is reset to 0 during start-up and stays at this
position until the write address exceeds the read address.
This is the case immediately after the input process starts.
The output process subsequently starts reading data at a
fixed data rate of 9 Mbit/s (AUDATCLK = 9 MHz, 67% duty
cycle (see Table 6 and Fig.10). The output process
continues outputting data as long as the read address
does not exceed the write address. If the read address
equals the write address the output stops (AUDATV is set
to logic 0) until new data is received at the input and the
write address counter increments again. Consequently, if
audio transport packets are equally distributed along the
transport stream, the FIFO remains almost empty.
The FIFO cannot overflow if the output rate equals at least
the average input rate. Given a capacity of 6 kByte for the
FIFO this means that at least 30 audio transport packets
can be stored before an overflow occurs.
Audio data can be downloaded by the microcontroller to
enable generation of ‘beeps’. For this purpose, the
demultiplexer has to be set to download mode (bit
‘ c_downl’ = 1, address 0x060A, see Table 13).
Parsing of audio transport packets with the proper PID
Suppression of transport packet header data
Detection of PES packet borders to find PES packet
length and PTS time stamps
Suppression of PES headers and stuffing bytes (bit
‘audio_pes’, address 0x060A, see Table 13), optional
Time expansion of the audio transport packet payload.
Preliminary specification
SAA7205H