SAA7205 Philips Semiconductors, SAA7205 Datasheet - Page 25

• Manufacturer Part Number: SAA7205
• Description: MPEG-2 systems demultiplexer
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.8
The audio interface performs system support for Philips
SAA2500 or third party audio decoders. The pin
assignment for the interface and a description of the
respective functions is given in Table 6. Audio PES or
elementary stream data are filtered by the audio data filter
and passed to a 6 kByte FIFO buffer in which they are
stored at the byte clock frequency (9 MHz). Audio
elementary stream data is read from the FIFO at the
AUDATCLK frequency. The frequency of this clock is
adapted to the audio bit rate index (32 to 448 kbit/s), which
is derived from audio frame header information. However,
to compensate for decoder delays, the output process is
conditioned to synchronize to presentation time stamps
(PTS).
The AUDECLK output is derived from the 27 MHz
demultiplexer chip clock through division by a real
number M, which is generated by programming I0 and I1
(words: ‘audio_incr0’, ‘audio_incr1’, addresses 0x060B
and 0x060C, see Table 13). The AUDECLK can be used
as an audio decoder chip clock and is generated by the
circuitry illustrated in Fig.14. The decoder clock is
generated with a maximum edge jitter of 37/2 = 18.5 ns.
Therefore, if this clock is used for audio digital-to-analog
conversion, for high quality audio it may have to be
dejittered using an external PLL or an LC filter.
Since most audio decoders accept only elementary audio
data, the demultiplexer takes care of the following basic
tasks in the audio path:
A block diagram of the audio interface circuitry is illustrated
in Fig.15.
One basic function of the audio data filter is to optionally
determine the audio frame length and find the frame
boundaries. The audio frame length depends on the basic
audio sampling frequency, the coded bit rate, the MPEG
layer used and in case of 44.1 kHz sampling frequency,
1997 Jan 21
Parsing of audio transport packets with the proper PID
Suppression of transport packet header data
Detection of PES packet boundaries to find PES packet
length and PTS time stamps
Suppression of PES headers and stuffing bytes (bit
‘audio_pes’, address 0x060A, see Table 13), optional
Detection of audio frame boundaries to find audio frame
length and audio bit rate, optional
Delay compensation and expansion of audio data to the
correct time and bit rate (bit ‘uc_sw_sync’, address
0x060A, see Table 13), optional.
MPEG-2 systems demultiplexer
Interfacing to SAA2500 and third party audio
decoders
25
the padding bit. The frame length ranges between
32 and 1728 bytes. All frame length related data are
coded in the audio frame header directly after the sync
word. Since the 12-bit sync word is not unique and could
be emulated in the audio stream, a recursive detection
algorithm consisting of the following steps is implemented:
1. Detect first occurrence of sync word
2. Evaluate header and determine frame length
3. If frame length is non valid go to step 1
4. Check whether a sync word exists at frame length
5. If no valid sync word is detected at this position go to
6. If sync word is valid go to step 2.
All relevant header parameters are stored in dedicated
registers. Their value is used for internal control but can
also be accessed by the external microcontroller (words:
‘audio_frame_length’, ‘audio_frame_info’, addresses
0x0611 and 0x0612, see Table 13).
The delay of the audio data from input to output of the
FIFO is basically determined by PTS time stamps. In order
to avoid difficult PTS management these time stamps are
stored in the FIFO between consecutive audio frames
(see Fig.15). If a PTS exists for one specific audio frame
the 23 least significant bits of the 33-bit time stamp are
stored together with a PTS_valid flag in three byte
positions preceding the associated audio frame. If no PTS
is available, three bytes are also inserted preceding the
audio frame, but in this case the PTS_valid flag indicates
that the remaining 23 bits may not be interpreted as a valid
PTS (see Fig.15).
The input process to the audio FIFO operates in stand
alone, but can be restarted by the microcontroller
(bit ‘ c_frc_restart’, address 0x060A, see Table 13).
During restart, the write address counter is reset to 0 and
kept at this position until the first audio frame with a valid
PTS is available from the stream. The storage of PTS plus
elementary audio data is then started. The storage
process continues as long as the detected audio frame
length remains the same. If a change in frame length
occurs, or if a sync word is missing, the write counter is
reset to 0 automatically and data storage is halted until a
valid audio frame with associated PTS is retrieved from the
stream. This kind of discontinuity handling is performed
unconditionally and is signalled to the external
microcontroller (interrupt: ‘irpt_audio_restart’, address
0x0000, see Table 13).
distance in the stream
step 1
Preliminary specification
SAA7205H