SAA7205 Philips Semiconductors, SAA7205 Datasheet - Page 65

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SAA7205

Manufacturer Part Number
SAA7205
Description
MPEG-2 systems demultiplexer
Manufacturer
Philips Semiconductors
Datasheet
Philips Semiconductors
Note
1. Actual input capacitance maximum value may change because of package selection.
1997 Jan 21
handbook, full pagewidth
SRAM interface (see Figs 49 and 50)
T
t
t
t
t
t
t
t
t
T
t
t
t
su(A)
h(A)
W
su(D-W)
h(D-W)
su(OE-RAMA)
AV
dat(Z-OE)
su(A-OE)
su(WE-OE)
d(DAT)(h)
SYMBOL
cy(W)
cy(R)
MPEG-2 systems demultiplexer
Fig.29 Timing definition of the synchronous input interface signals with the SAA7206 (descrambler).
DCLK
PKTDAT7 to PKTDAT0
PKTDATV
PKTBAD/PKTBAD
PKTSYNC
write cycle time
address set-up to write enable
WE inactive to end of RAMA
pulse width
data set-up to write end
data hold from write end
OE to RAM A set-up time
address valid time
data 3-state to OE inactive
read cycle time
address set-up to OE
WE to OE set-up time
data hold delay time
PARAMETER
t i(r)
t i(r)(DCLK)
t i(su)
t i(f)
t i(h)s
t DCLKH
CONDITIONS
65
T cy(DCLK)
t i(f)(DCLK)
t DCLKL
86
12
12
35
32
12
69
12
123
10
0
5
MIN.
98
28
+5
24
135
24
60
Preliminary specification
MAX.
SAA7205H
MGG789
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UNIT

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