SAA7205 Philips Semiconductors, SAA7205 Datasheet - Page 20

• Manufacturer Part Number: SAA7205
• Description: MPEG-2 systems demultiplexer
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.7
Communication to a third party video decoder involves
merging both video packetized elementary stream (PES)
or elementary stream (ES) data and control data on the
same 8-bit bidirectional bus VO7 to VO0 (see Fig.10).
PES or ES (bit: ‘video_pes_esn’, address 0x050A, see
Table 13) data is filtered by the video data filter and is
passed to a 768 Byte video FIFO buffer (see Section
“Output buffering for audio and video”), in which it is stored
at byte clock frequency (9 MHz). The video PES or ES
stream is read from the FIFO at video data acquisition
clock frequency CLKP (equals 9 MHz = CCLKI/3, 67%
duty cycle, see Fig.10). However, CLKP is a gated clock
signal, which is frozen to logic 1 in case of control
exchange between the microcontroller and the video
decoder (
A bidirectional bus multiplexer (‘Merger’) is therefore
located at the output of the video FIFO. The timing
associated with the video output interface is illustrated in
Fig.11.
1997 Jan 21
handbook, full pagewidth
MPEG-2 systems demultiplexer
GPO7 to GPO0
Interfacing to a third party video decoder
GPSYNC
GPST
VSEL = 0), or FIFO underflow (see Fig.10).
GPV
byte 187
Fig.9 Signal constellation for general purpose interface (SAA7201 compatible).
consecutive transport packet bytes
sync byte (0)
t CLKOH
t CLKOL
20
The third party video interface outputs clock and
synchronization references. The set of references consists
of a 13.5 MHz clock (CLK13.5, programmable phase, bit:
‘clk_13p5_pol’, address 0x050A, see Table 13), a CbREF
signal, “CCIR 601” compliant H, V, composite syncs, and
a field parity (EVEN/ODD) signal (both 50 Hz and 60 Hz,
bit: ‘ccir_50_60n’, address 0x050A, see Table 13).
The CbREF signal is locked to CCLKI and indicates
U samples in the UY/VY video decoder output.
To compensate for the delay in the decoding path, the
phase of CbREF (active LOW) is programmable as
illustrated in Fig.13 [bits: cb_ref_phase (1 to 0)], address
0x050A, see Table 13). The clock period immediately
following a COMSYNC falling edge in normal lines (equals
HSYNC falling edge) corresponds to counter position 0,
the clock period preceding the falling edge corresponds to
position 1727 (50 Hz), or 1715 (60 Hz),
byte 1
Preliminary specification
SAA7205H
bytes 2 to 187
MGG770