SAA7205 Philips Semiconductors, SAA7205 Datasheet - Page 17

• Manufacturer Part Number: SAA7205
• Description: MPEG-2 systems demultiplexer
• Manufacturer: Philips Semiconductors

Philips Semiconductors
7.4
An optional external descrambler can be incorporated in a digital TV receiver in the configuration indicated in Fig.7.
In such a configuration the demultiplexer generates a 9 MHz, 33% duty cycle descrambler clock (DCLK) signal
(see Fig.5). A descrambler could use this clock signal for data processing and outputting data. In such a configuration
the demultiplexer input interface is set to 9 MHz mode (bit 9 MHz_interface = 1, address 0x0100, see Table 13).
1997 Jan 21
handbook, full pagewidth
MPEG-2 systems demultiplexer
Interfacing to the external descrambler
FORWARD ERROR
DEMODULATOR
CORRECTOR
AND
Fig.7 Digital TV receiver configuration including a descrambler.
DESCRAMBLER
OPTIONAL
MICROCONTROLLER
DCLK (9 MHz)
SYSTEM
17
DEMULTIPLEXER
SAA7205H
MPEG2
APPLICATIONS
TELETEXT
DECODER
DECODER
H/S DATA
VIDEO
AUDIO
AND
Preliminary specification
MGG767
SAA7205H