XC7336-10 Xilinx, XC7336-10 Datasheet - Page 4

• Manufacturer Part Number: XC7336-10
• Description: 36-Macrocell CMOS EPLD
• Manufacturer: Xilinx

XC7336 CMOS EPLD
Power Management
The XC7336 features a power-management scheme
which permits non-speed-critical paths of a design to be
operated at reduced power. Overall power dissipation is
often reduced significantly, since, in most systems only a
few paths are speed critical.
Macrocells can individually be specified for high perfor-
mance or low power operation by adding attributes to the
logic schematic, or declaration statements to the behavioral
description. To minimize power dissipation, unused Func-
tion Blocks are turned off and unused Macrocells in used
Function Blocks are configured for low power operation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
For non-Q devices:
For Q devices: (-10, -12, -15):
Where:
Figure 4 shows a typical power calculation for the XC7336
device, programmed as two 16-bit counters and operating
at the indicated clock frequency.
Figure 4. Typical I
MC
MC
MC
f
I
I
CC
CC
MC (0.005 mA/MHz) f
MC (0.005 nA/MHz) f
(mA) = MC
HP
LP
(mA) = MC
200
150
100
50
= Macrocells in high-performance mode
= Macrocells in low-power mode
= Total number of Macrocells used
= Clock frequency (MHz)
0
CC
HP
HP
vs Frequency for XC7336
Clock Frequency (MHz)
(4.3) + MC
(2.0) + MC
50
LP
LP
(3.5) +
(1.6) +
X5767
100
2-26
Design Security
The XC7336 has a multibit security system that controls
access to the configuration programmed into the device.
This security scheme uses multiple EPROM bits at vari-
ous locations within the EPROM array to offer a higher
degree of design security than other EPROM and fused-
based devices.
Prototyping and Programming
Xilinx offers the HW-120 programmer for use during
prototyping as well as support from major third party
programmer companies. For production volumes, Xilinx and
their licensed distributors offer factory programming of the
XC7336 devices.
For factory programming procedures, contact your local
Xilinx representative.
XEPLD Translator Software
The designer can create, implement, and verify digital logic
circuits for EPLD devices using the Xilinx XEPLD software.
Designs can be represented as schematics consisting of
XEPLD library components, as behavioral descriptions
(Boolean, HDL etc.), or as a combination of both tech-
niques. The XEPLD translator automatically optimizes, col-
lapses, and implements the design as well as writing a
programming file without user intervention. At the comple-
tion of the compilation process, the XEPLD translator
writes detailed report files for design analysis and docu-
mentation.