S29WS-P SPANSION [SPANSION], S29WS-P Datasheet
S29WS-P
Related parts for S29WS-P
S29WS-P Summary of contents
Page 1
... Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S29WS-P_00 Notice On Data Sheet Designations Revision A Amendment 7 S29WS-P Cover Sheet for definitions. Issue Date November 8, 2006 ...
Page 2
... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S29WS S29WS-P_00_A7 November 8, 2006 ...
Page 3
... OE Publication Number S29WS-P_00 This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. ...
Page 4
... Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.1 Factory Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.2 Customer Secured Silicon Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 11. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S29WS S29WS-P_00_A7 November 8, 2006 ...
Page 5
... Chip Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Table 7.30 Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 7.31 Erase Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Table 7.32 Unlock Bypass Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 7.33 Unlock Bypass Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 7.34 Unlock Bypass Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 7.35 DQ6 and DQ2 Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Table 7.36 Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 November 8, 2006 S29WS-P_00_A7 ( S29WS-P 3 ...
Page 6
... Figure 11.14 Reset Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 11.15 Asynchronous Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 11.16 Synchronous Program Operation Timings Figure 11.17 Chip/Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 11.18 Accelerated Unlock Bypass Programming Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S29WS S29WS-P_00_A7 November 8, 2006 ...
Page 7
... Figure 11.20 Toggle Bit Timings (During Embedded Algorithm Figure 11.21 Synchronous Data Polling Timings/Toggle Bit Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 11.22 DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 11.23 Latency with Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 11.24 Wait State Configuration Register Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 11.25 Back-to-Back Read/Write Cycle Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 November 8, 2006 S29WS-P_00_A7 ( S29WS-P 5 ...
Page 8
... Package Type, Material, & Status Option Temperature Range BAW (Lead (Pb)-free 0L, 0P, Compliant), 0S, AB BFW (Lead (Pb)-free) S29WS Packing Model Package Type Type Numbers (Note 2) 11 84-ball MCP-Compatible (Note 1) 11 84-ball MCP-Compatible S29WS-P_00_A7 November 8, 2006 ...
Page 9
... RESET# Input WP# Input ACC Input RFU Reserved November 8, 2006 S29WS-P_00_A7 ( Table 2.1 Input/Output Descriptions Description Address lines (Amax = 24 for WS512P 1CE# option, 23 for WS512P 2CE# option, 23 for WS256P, and 22 for WS128P) Data input/output. ...
Page 10
... This section shows the I/O designations and package specifications for the #. 4.1 Related Documents The following documents contain information relating to the S29WS-P devices. Click on the title www.spansion.com to download the PDF file, or request a copy from your sales office. Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits 4 ...
Page 11
... DNU Notes: 1. Balls F6 and G8 are RFU on the WS128P. 2. Ball G8 is RFU on the WS256P. November 8, 2006 S29WS-P_00_A7 ( Figure 4.1 84-Ball Fine-Pitch Ball Grid Array, 512, 256 & 128 Mb (Top View, Balls Facing Down, MCP Compatible) ...
Page 12
... WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. S29WS-P_00_A7 November 8, 2006 ...
Page 13
... CE#f1 K2 CE1# VCCnds M2 A27 November 8, 2006 S29WS-P_00_A7 ( Figure 4.3 MCP Look-ahead Diagram 96-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down VSSds CLK CE#f2 VCCds RESET#ds ...
Page 14
... Spansion Japan Limited Cube-Kawasaki 9F/10F, 1-14 Nisshin-cho, Kawasaki-ku, Kawasaki-shi, Kanagawa, 210-0024, Japan Phone: 044-223-1700 (active from Nov.28th) http://www.spansion.com obtain the following related documents: S29WS S29WS-P_00_A7 November 8, 2006 ...
Page 15
... Product Overview The S29WS-P family consists of 512, 256, and 128 Mbit, 1.8 volts-only, simultaneous read/write burst mode Flash device optimized for today’s wireless designs that demand a large storage array, rich functionality, and low power consumption. These devices are organized in 32, 16 Mwords of 16 bits each and are capable of continuous, synchronous (burst) read or linear read (8-, 16-, or 32-word aligned group) with or without wrap around ...
Page 16
... SA261 FFC000h–FFFFFFh S29WS Address Range Notes Contains four smaller sectors at bottom of addressable memory. All 128 KB sectors. Pattern for sector address range is xx0000h–xxFFFFh. (see note) Contains four smaller sectors at top of addressable memory. S29WS-P_00_A7 November 8, 2006 ...
Page 17
... Writing incorrect address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command to return the device to the reading array data mode. November 8, 2006 S29WS-P_00_A7 ( Table 6.3 S29WS128P Sector & ...
Page 18
... Valid Addr In I HIGH Z HIGH HIGH Z HIGH Z Output L Addr In X Invalid Output Valid X X HIGH Z HIGH HIGH Z HIGH Z Output Addr In X Invalid = high to low, = toggle. –A0, while driving AVD# max S29WS-P_00_A7 November 8, 2006 ...
Page 19
... The following tables show the latency for variable wait state in a normal Burst operation Word Initial Wait November 8, 2006 S29WS-P_00_A7 ( and subsequent page read accesses (as long as the ACC CE Table 7.2 Page Select Word A2 Word 0 0 ...
Page 20
... D11 D10 D11 D10 D10 D11 D8 D9 D10 D11 D12 D8 D9 D10 D11 D12 D8 D9 D10 D11 D12 D8 D9 D10 D11 D12 S29WS-P_00_A7 November 8, 2006 ...
Page 21
... November 8, 2006 S29WS-P_00_A7 ( Table 7.8 Address Latency for 4 Wait States ...
Page 22
... D14 D15 D16 D17 D18 D12 D13 D14 D15 D16 D17 D18 D12 D13 D14 D15 D16 D17 D18 S29WS-P_00_A7 November 8, 2006 D15 D16 D16 D17 D16 D17 D16 D17 D16 D17 D16 D17 D16 D17 D16 D17 D15 D16 D16 ...
Page 23
... November 8, 2006 S29WS-P_00_A7 ( Table 7.16 Address Latency for 4 Wait States ...
Page 24
... Hardware Reset Asynchronous Read Mode Only Set Burst Mode Set Burst Mode Configuration Register Configuration Register Command for Synchronous Mode Asynchronous Mode (CR15 = 0) Synchronous Read Mode Only S29WS 78, for further Command for (CR15 = 1) S29WS-P_00_A7 November 8, 2006 ...
Page 25
... If the address crosses a bank boundary while the subsequent bank is programming or erasing, the device provides read status information and the clock is ignored. Upon completion of status read or program or erase operation, the host can restart a burst read operation using a new address and AVD# pulse. November 8, 2006 S29WS-P_00_A7 ( Figure 7 ...
Page 26
... Table 7.19 Burst Address Groups Group Size 8 words 0-7h, 8-Fh, 10-17h,... 16 words 0-Fh, 10-1Fh, 20-2Fh,... 32 words 00-1Fh, 20-3Fh, 40-5Fh,... S29WS Table 7.19). Group Address Ranges S29WS-P_00_A7 November 8, 2006 ...
Page 27
... CR0.3 is ignored if in continuous read mode (no warp around software reset command is required after reading or writing the configuration registers in order to set the device back to array read mode. 5. Refer to Table 12.1 on page 78 November 8, 2006 S29WS-P_00_A7 ( Table 7.20 Configuration Register Settings (Binary) ...
Page 28
... DQ6 -Customer Lock Bit Locked Not Locked DQ5 - Handshake Bit Reserved Standard Handshake DQ4 & DQ3 - WP# Protection Boot Code WP# Protects both Top Boot and Bottom Boot Sectors, DQ2 - DQ0 = reserved 223Dh (WS512P)-1CE# 2242h (WS256P) 2244h (WS128P) 2200h S29WS-P_00_A7 November 8, 2006 ...
Page 29
... Autoselect exit */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */ November 8, 2006 S29WS-P_00_A7 ( Table 7.22 Autoselect Entry (LLD Function = lld_AutoselectEntryCmd) ...
Page 30
... Write Buffer Programming on page (Table 7.20 on page when providing an address to the device, and drive WE# and CE when using the write buffer. S29WS 25). IL Write Operation Status S29WS-P_00_A7 November 8, 2006 , and ...
Page 31
... The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Operation successfully completed November 8, 2006 S29WS-P_00_A7 ( for the required bus cycles and Figure 7 ...
Page 32
... S29WS Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 00A0h Word Address Data Word */ */ */ */ S29WS-P_00_A7 November 8, 2006 ...
Page 33
... Last = Last cycle of write buffer program operation; depending on number of words written, the total number of cycles may be from 6 to 37. 3. For maximum efficiency recommended that the write buffer be loaded with the highest number of words (N words) possible. November 8, 2006 S29WS-P_00_A7 ( Table 7 ...
Page 34
... Example: Write Buffer Abort Reset */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; /* write unlock cycle (UINT16 *)base_addr + 0x2AA ) = 0x0055; /* write unlock cycle (UINT16 *)base_addr + 0x555 ) = 0x00F0; /* write buffer abort reset */ S29WS S29WS-P_00_A7 November 8, 2006 ...
Page 35
... The system may also write the Autoselect command sequence when the device is in Program Suspend mode. The device allows reading Autoselect codes in the suspended sectors, since the codes are not stored November 8, 2006 S29WS-P_00_A7 ( Figure 7 ...
Page 36
... Word Address Data Bank Address 00B0h /* write suspend command Word Address Data Bank Address 0030h /* write resume command Table 12.1 on page 78 occurs. During the time- SEA . Any sector erase address and command for information on these status S29WS-P_00_A7 November 8, 2006 PRS */ */ and ...
Page 37
... November 8, 2006 S29WS-P_00_A7 ( illustrates the algorithm for the erase operation. Refer to Table 7.28 Sector Erase ...
Page 38
... No limit on number of sectors • Commands other than Erase Suspend or selecting additional sectors for erasure during timeout reset device to reading array data Status may be obtained by reading DQ7, DQ6 and/or DQ2. Error condition (Exceeded Timing Limits) S29WS-P_00_A7 November 8, 2006 timeout to ensure ...
Page 39
... November 8, 2006 S29WS-P_00_A7 ( Table 12.1 on page for information on these status bits. Table 7.29 Chip Erase ...
Page 40
... Bank Address /* write resume command S29WS time-out period during the sector erase for information on these status bits. for details. Word Address Data Bank Address 00B0h Word Address Data Bank Address 0030h S29WS-P_00_A7 November 8, 2006 ERS */ */ ...
Page 41
... Refer to Erase/Program Timing on page 69 on page 71 for timing diagrams. November 8, 2006 S29WS-P_00_A7 ( this input, the device automatically enters the accelerated mode and uses the HH from the ACC input, upon completion of the HH ...
Page 42
... Base + xxxh S29WS Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 0020h */ */ */ */ */ */ */ */ Word Address Data Base +xxxh 00A0h Program Address Program Data */ */ Word Address Data Base +xxxh 0090h Base +xxxh 0000h S29WS-P_00_A7 November 8, 2006 ...
Page 43
... DQ7 has valid data, the data outputs on DQ6-DQ1 may be still invalid. Valid data on DQ7-DQ1 appears on successive read cycles. See the following for more information: Figure 7.6 on page Polling timing diagram. November 8, 2006 S29WS-P_00_A7 ( then the bank returns to the read mode. If not all selected sectors are ASP Table 7.36 on page 42, shows the Data# Polling algorithm ...
Page 44
... S29WS Erase Operation Complete YES Read 2 Read3= valid data? NO Read 3 Program Operation Failed YES Programming Operation? NO (Note 5) (Note 1) YES DQ6 DEVICE toggling? ERROR NO (Note 2) YES DQ2 toggling? NO Erase Device in Operation Erase/Suspend Complete Mode S29WS-P_00_A7 November 8, 2006 ...
Page 45
... Read address has to be relatched by toggling AVD# for each reading cycle. If device is programming, actively erasing, erase suspended, programming in erase suspend November 8, 2006 S29WS-P_00_A7 ( Figure 7.6 on page 45. Table 7.35 DQ6 and DQ2 Indications and the system reads ...
Page 46
... See Write Buffer Programming Operation for more details Table 7.36 on page 45 S29WS Figure 7.6 , the system need not monitor DQ3. See SEA shows the status of DQ3 relative to the S29WS-P_00_A7 November 8, 2006 ...
Page 47
... Similarly, a sector address is the address bits required to uniquely select a sector. I the write mode. AC Characteristics-Synchronous and AC Characteristics-Asynchronous contain timing specification tables and timing diagrams for write operations. November 8, 2006 S29WS-P_00_A7 ( Table 7.36 Write Operation Status ...
Page 48
... Table 12.1 on page Table 7.37 Reset (LLD Function = lld_ResetCmd) Operation Byte Address Write Base + xxxh S29WS RESET# is held at V CC4 IL 78) that also returns the device to array Word Address Data Base + xxxh 00F0h S29WS-P_00_A7 November 8, 2006 , but ...
Page 49
... CR1.4. It allows 2 programmable slew rates. This feature is for users who do not wish to run the part at its maximum frequency. Mode 1 2 November 8, 2006 S29WS-P_00_A7 ( Table 7.38 Programmable Output Slew Rate Description ...
Page 50
... Dynamic Protection Bit (DYB) 6,7,8 DYB 0 DYB 1 DYB 2 DYB N-2 DYB N-1 DYB Sector Protected Sector Unprotected. 7. DYB bits are only effective for sectors that not protected via PPB locking mechanism. 8. Volatile Bits: defaults to unprotected after power up. S29WS-P_00_A7 November 8, 2006 ...
Page 51
... Reads from other banks (simultaneous operation) are not allowed during lock register programming. This restriction applies to both synchronous and asynchronous read operations. November 8, 2006 S29WS-P_00_A7 ( Table 8.1 Sector Protection Schemes ...
Page 52
... During PPB program / erase data polling can be done synchronously. 13. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode S29WS Figure 8.2 on page 51. S29WS-P_00_A7 November 8, 2006 ...
Page 53
... November 8, 2006 S29WS-P_00_A7 ( PPB Program/Erase Algorithm Figure 8.2 Enter PPB Command Set. Addr = BA Program PPB Bit. Addr = SA0 Read Byte Twice Addr = SA0 No DQ6 = Toggle? Yes No DQ5 = 1? Yes Read Byte Twice ...
Page 54
... The PPB Lock Bit must be set (programmed to 0) only after all PPBs are configured to the desired settings Table 8.1 on page S29WS 49). S29WS-P_00_A7 November 8, 2006 ...
Page 55
... The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device. November 8, 2006 S29WS-P_00_A7 ( ...
Page 56
... S29WS Unlock Cycle 1 Unlock Cycle 2 XXXh = Address don’t care * Not on future devices Program Data (PD): See text for Lock Register definitions Caution: Lock register can only be progammed once. Error condition (Exceeded Timing Limits) S29WS-P_00_A7 November 8, 2006 ...
Page 57
... The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until V proper signals to the control inputs to prevent unintentional writes when V November 8, 2006 S29WS-P_00_A7 ( Table 8 ...
Page 58
... V, the standby current is greater. , output from the device is disabled. The outputs are placed in the high IH S29WS for read access, before it CE represents the standby + 20 ns. ACC in DC Characteristics on page 61 represents ). If RESET# is held at CC4 S29WS-P_00_A7 November 8, 2006 ...
Page 59
... ESN. The devices are then shipped from the Spansion factory with the Factory Secured Silicon Sector and Customer Secured Silicon Sector permanently locked. Contact your local representative for details on using Spansion programming services. November 8, 2006 S29WS-P_00_A7 ( Table 10 ...
Page 60
... Base + AAAh Write Base + 554h Write Base + AAAh /* write unlock cycle 1 /* write unlock cycle 2 /* write Secured Silicon Sector Entry Cmd S29WS Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 0088h */ */ S29WS-P_00_A7 November 8, 2006 ...
Page 61
... Example: Secured Silicon Sector Exit Command */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; *( (UINT16 *)base_addr + 0x555 ) = 0x0090 (UINT16 *)base_addr + 0x000 ) = 0x0000 November 8, 2006 S29WS-P_00_A7 ( Table 10.3 Secured Silicon Sector Program (LLD Function = lld_ProgramCmd) Operation Byte Address ...
Page 62
... V CC +0 S29WS –65°C to +150°C –65°C to +125°C –0 2.5 V –0 +2.5 V –0 +9.5 V 100 mA to –2.0 V for periods –2.0 V for periods ns S29WS-P_00_A7 November 8, 2006 CC ...
Page 63
... Device enters automatic sleep mode when addresses are stable for t 4. Total current during accelerated programming is the sum during all ICC measurements. CCQ <Helv>± 0.2V and November 8, 2006 S29WS-P_00_A7 ( Ambient Temperature ( Supply Voltages CC Description Test Conditions V ...
Page 64
... S29WS All Speed Options 30 1.0 - 1.50 0.0– Outputs Steady Changing, State Unknown Center Line is High Impedance State (High Output CC Test Setup Time Unit Min 30 Min 200 S29WS-P_00_A7 November 8, 2006 Unit µs ns ...
Page 65
... CLK t CLK Period CLK t /t CLK Low/High Time CLK Rise Time CR t CLK Fall Time CF CLK November 8, 2006 S29WS-P_00_A7 ( Figure 11.5 V Power-up Diagram CC t VCS V CC min 54 MHz 66 MHz Max 54 66 Min Min 18 ...
Page 66
... MHz 80 13.5 11 13.5 11 13.5 11 Clock to Out) BACC Wait State Requirement S29WS-P_00_A7 November 8, 2006 Unit ...
Page 67
... Figure shows for illustration the total number of wait states set to seven cycles. 2. The device is configured synchronous single data rate mode and RDY active with data. 3. CE# (High) drives the RDY to Hi-Z while OE# (High) drives the DQ(15:0) pins to HI-Z. November 8, 2006 S29WS-P_00_A7 ( ...
Page 68
... OE t WEA t OEH AAVDH AAVDS S29WS Asynchronous Max 83 Max 80 Min 7.5 Min 6 Min 0 Max 13.5 Min 0 Min 4 Max 7.6 Min 0 Max 20 Max 7.6 t CEZ t OEZ RD t CEZ Hi-Z S29WS-P_00_A7 November 8, 2006 Unit ...
Page 69
... Notes: 1. AVD# Transition occurs after CE# is driven to Low and AVD# is driven low before Valid Address Transition Valid Read Address Read Data. November 8, 2006 S29WS-P_00_A7 ( Figure 11.10 Asynchronous Read Mode (AVD# Toggling - Case 2) ...
Page 70
... ACC Qa Table 11.4 Hardware Reset Description RESET# Pulse Width Reset High Time Before Read S29WS CEZ t OEZ CEZ PACC PACC PACC All Speed Options Min 30 Min 200 S29WS-P_00_A7 November 8, 2006 Hi-Z Unit µs ns ...
Page 71
... In programming operations, addresses are latched on the active edge of CLK for programming synchronously or rising edge of AVD# for programming asynchronously. 3. See the Erase and Programming Performance on page 77 November 8, 2006 S29WS-P_00_A7 ( Reset Timings Figure 11.14 ...
Page 72
... Figure 11.15 Asynchronous Program Operation Timings Program Command Sequence (last two cycles) t AVDP 555h A0h CAS WPH VCS S29WS Read Status Data Complete Progress WHWH1 S29WS-P_00_A7 November 8, 2006 ...
Page 73
... PA = Program Address Program Data Valid Address for reading status bits progress and complete refer to status of program operation. 3. Addresses are latched on the first rising edge of CLK. November 8, 2006 S29WS-P_00_A7 ( Figure 11.16 Synchronous Program Operation Timings ...
Page 74
... WPH t WC Figure 11.18 Accelerated Unlock Bypass Programming Timing Don't Care A0h Don't Care t 1 µs VIDS S29WS Read Status Data Complete Progress t WHWH2 PA PD Don't Care S29WS-P_00_A7 November 8, 2006 ...
Page 75
... Status reads in figure are shown as asynchronous Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. November 8, 2006 S29WS-P_00_A7 ( Figure 11.19 Data# Polling Timings (During Embedded Algorithm) ...
Page 76
... IACC Status Data Figure 11.22 DQ2 vs. DQ6 Erase Enter Erase Suspend Suspend Program Erase Erase Suspend Erase Suspend Read Program S29WS IACC Status Data Erase Resume Erase Erase Erase Suspend Complete Read S29WS-P_00_A7 November 8, 2006 ...
Page 77
... Figure shows the device not crossing a bank in the process of performing an erase or program. Data AVD# OE# CLK 0 November 8, 2006 S29WS-P_00_A7 ( Figure 11.23 Latency with Boundary Crossing Address boundary occurs every 128 words, beginning at address 00007Fh: (0000FFh, 00017Fh, etc.) Address 000000h is also a boundary crossing. ...
Page 78
... Sector Erase Command Sequence OEH t OEZ ACC PD/30h RD t SR/W PA/ S29WS Begin another write or program command sequence GHWL t OEH RD AAh RA 555h S29WS-P_00_A7 November 8, 2006 ...
Page 79
... Table 12.2 on page 80 11.9.1 BGA Ball Capacitance Parameter Symbol Output Capacitance OUT Notes 1. Sampled, not 100% tested. 2. Test conditions t - 25° 1.0 MHz A November 8, 2006 S29WS-P_00_A7 ( Typ (Note 1) 64 Kword V 0 Kword V 0.35 CC 78.4 (WS128P) V 155 ...
Page 80
... X00 (BA) (BA)X (BA) 90 227E (10) 0E X0F X01 (BA) 90 (12) X03 (SA) 0000/ 90 X02 0001 A0 PA Data WBL (20 555 AA 2AA 55 555 80 555 AA 2AA X00 CR0 X01 CR1 S29WS-P_00_A7 November 8, 2006 Sixth Data (19) (10 ...
Page 81
... Data is always output at the rising edge of clock. 20. Must be the lowest address. 21. Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration registers will retain their previous settings November 8, 2006 S29WS-P_00_A7 ( 26. ...
Page 82
... (BA (BA) RD( S29WS Fourth Fifth Sixth Data( Data( Data( (10) Addr (10) Addr (10) Addr PWD 03 3 PWD PWD PWD S29WS-P_00_A7 November 8, 2006 Seventh Data( (10 ...
Page 83
... PPB Erase” command pre-programs all PPBs before erasure to prevent over-erasure. 9. Entire two bus-cycle sequence must be entered for each portion of the password. 10. Full address range is required for reading password. November 8, 2006 S29WS-P_00_A7 ( ...
Page 84
... Max. time for full chip erase [2 S29WS Description Description pin present) pin present) N µs (e.g. 30us) N µs (e.g. 300us) (00h = not supported (00h = not supported) N times typical value] N times typical value] times typical value] (00h = not supported) S29WS-P_00_A7 November 8, 2006 */ */ ...
Page 85
... November 8, 2006 S29WS-P_00_A7 ( Table 12.5 Device Geometry Definition Data 0018h (WS128P) N 0019h (WS256P) Device Size = 2 byte 001Ah (WS512P) 0001h Flash Device Interface 0h=x8; 1h=x16; 2h=x8/x16; 3h=x32 [lower byte] ...
Page 86
... Bank 2 Region Information Number of sectors in bank 0010h (WS256P) 0020h (WS512P) 0008h (WS128P) 0010h (WS256P) Bank 3 Region Information Number of sectors in bank 0020h (WS512P) S29WS Description N bytes N µs N µs S29WS-P_00_A7 November 8, 2006 N ...
Page 87
... November 8, 2006 S29WS-P_00_A7 ( Table 12.6 Primary Vendor-Specific Extended Query (Sheet Data 0008h (WS128P) 0010h (WS256P) Bank 4 Region Information Number of sectors in bank 0020h (WS512P) ...
Page 88
... and V ramp rates (must be simultaneous) CC CCQ specification CCB Specification updated CC2 CC Sleep Current CC to table 11.8.2 CEZ for Asynchronous AVWL = AAVDS = 13 Test Setup to "Min" RH row from table AS S29WS Description S29WS-P_00_A7 November 8, 2006 ...
Page 89
... Copyright © 2005-2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. November 8, 2006 S29WS-P_00_A7 ( ...