S29WS-P SPANSION [SPANSION], S29WS-P Datasheet - Page 47

• Manufacturer Part Number: S29WS-P
• Description: 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory
• Manufacturer: SPANSION [SPANSION]

7.8
7.9
November 8, 2006 S29WS-P_00_A7
Simultaneous Read/Program or Erase
Writing Commands/Command Sequences
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. Data are invalid for addresses in a Program Suspended sector.
4. DQ1 indicates the Write to Buffer ABORT status during Write Buffer Programming operations.
5. The data-bar polling algorithm should be used for Write Buffer Programming operations. Note that DQ7# during Write Buffer
The simultaneous read/program or erase feature allows the host system to read data from one bank of
memory while programming or erasing another bank of memory. An erase operation may also be suspended
to read from or program another location within the same bank (except the sector being erased).
on page 76
Refer to
When the device is configured for Asynchronous read, only Asynchronous write operations are allowed, and
CLK is ignored. When in the Synchronous read mode configuration, the device is able to perform both
Asynchronous and Synchronous write operations. CLK and AVD# induced address latches are supported in
the Synchronous programming mode. During a synchronous write operation, to write a command or
command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive AVD# and CE# to V
WE# and CE# to V
operation, the system must drive CE# and WE# to V
and data. Addresses are latched on the last falling edge of WE# or CE#, while data is latched on the 1st rising
edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or the entire device.
Table 6.2 on page 14
device address space is divided into sixteen banks: Banks 1 through 14 contain only 64 Kword sectors, while
Banks 0 and 15 contain both 16 Kword boot sectors in addition to 64 Kword sectors. A bank address is the set
of address bits required to uniquely select a bank. Similarly, a sector address is the address bits required to
uniquely select a sector. I
the write mode. AC Characteristics-Synchronous and AC Characteristics-Asynchronous contain timing
specification tables and timing diagrams for write operations.
Standard
Suspend
Suspend
Program
(Note 3)
(Note 5)
Write to
section on DQ5 for more information.
Programming indicates the data-bar for DQ7 data for the LAST LOADED WRITE-BUFFER ADDRESS location.
Erase
Buffer
Mode
Mode
Mode
D a t a
DC Characteristics on page 61
Embedded Program Algorithm
Embedded Erase Algorithm
Reading within Program Suspended Sector
Reading within Non-Program Suspended
Sector
Erase-Suspend-
Read
Erase-Suspend-Program
BUSY State
Exceeded Timing Limits
ABORT State
shows how read and write cycles may be initiated for simultaneous operation with zero latency.
S h e e t
IL
, and OE# to V
Status
and
CC2
( A d v a n c e
Table 6.3 on page 15
Erase
Suspended Sector
Non-Erase Suspended
Sector
in
DC Characteristics on page 61
IH
Table 7.36 Write Operation Status
when writing commands or data. During an asynchronous write
IL
, and OE# to V
S29WS-P
for read-while-program and read-while-erase current specification.
I n f o r m a t i o n )
(Note 2)
INVALID
Allowed)
indicate the address space that each sector occupies. The
DQ7#
DQ7#
DQ7#
DQ7#
DQ7#
DQ7
Data
Data
(Not
0
1
IL
and OE# to V
IH
when providing an address to the device, and drive
No toggle
INVALID
Allowed)
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
DQ6
Data
Data
(Not
represents the active current specification for
IH
INVALID
Allowed)
(Note 1)
when providing an address, command,
DQ5
Data
Data
(Not
0
0
0
0
0
1
0
INVALID
Allowed)
DQ3
Data
Data
(Not
N/A
N/A
N/A
N/A
N/A
N/A
1
No toggle
INVALID
Allowed)
(Note 2)
Toggle
Toggle
DQ2
Data
Data
(Not
N/A
N/A
N/A
N/A
Figure 11.25
INVALID
Allowed)
(Note 4)
DQ1
Data
Data
(Not
N/A
N/A
N/A
0
0
0
1
45