S29WS-P SPANSION [SPANSION], S29WS-P Datasheet - Page 9
![no-image](/images/no-image-200.jpg)
S29WS-P
Manufacturer Part Number
S29WS-P
Description
512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S29WS-P.pdf
(89 pages)
- Current page: 9 of 89
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2.
November 8, 2006 S29WS-P_00_A7
Input/Output Descriptions & Logic Symbol
Table identifies the input and output package connections provided on the device.
DQ15–DQ0
A
RESET#
D a t a
Symbol
MAX
AVD#
V
WE#
WP#
OE#
RDY
ACC
RFU
CE#
V
CLK
V
NC
CCQ
CC
SS
–A0
S h e e t
No Connect
Reserved
Supply
Supply
Output
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
( A d v a n c e
Address lines (Amax = 24 for WS512P 1CE# option, 23 for WS512P 2CE# option, 23 for WS256P, and
22 for WS128P)
Data input/output.
Chip Enable. Asynchronous relative to CLK.
Output Enable. Asynchronous relative to CLK.
Write Enable.
Device Power Supply
Device Power Supply (Must be ramped simultaneously with V
Ground.
Not connected internally.
Ready. Indicates when valid burst data is ready to be read.
Clock Input. In burst mode, after the initial word is output, subsequent active edges of CLK increment
the internal address counter. Should be at V
Address Valid. Indicates to device that the valid address is present on the address inputs.
When low during asynchronous mode, indicates valid address; when low during burst mode, causes
starting address to be latched at the next active clock edge.
When high, device ignores address inputs.
Hardware Reset. Low = device resets and returns to reading array data.
Write Protect. At V
V
Acceleration Input. At V
mode. At V
Reserved for future use (see MCP look-ahead pinout for use with MCP).
IH
for all other conditions.
Table 2.1 Input/Output Descriptions
IL
, disables all program and erase functions. Should be at V
S29WS-P
IL
I n f o r m a t i o n )
, disables program and erase functions in the four outermost sectors. Should be at
HH
, accelerates programming; automatically places device in unlock bypass
IL
Description
or V
IH
while in asynchronous mode.
CC
)
IH
for all other conditions.
7
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