S29WS-P SPANSION [SPANSION], S29WS-P Datasheet - Page 66

• Manufacturer Part Number: S29WS-P
• Description: 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory
• Manufacturer: SPANSION [SPANSION]

11.8
64
11.8.1
AC Characteristics
Synchronous/Burst Read
Notes:
1. Addresses are latched on the rising edge of CLK
2. Synchronous Access Time is calculated using the formula (#of WS - 1)*(clock period) + (t
JEDEC
Parameter
95 MHz < Frequency ≤ 108 MHz
27 MHz < Frequency ≤ 40 MHz
40 MHz < Frequency ≤ 54 MHz
54 MHz < Frequency ≤ 67 MHz
67 MHz < Frequency ≤ 80 MHz
80 MHz < Frequency ≤ 95 MHz
14 < Frequency ≤ MHz
Frequency ≤ 14 MHz
Standard
Max Frequency
t
t
t
BACC
t
t
t
t
t
t
RACC
t
t
t
t
IACC
ACH
BDH
t
ACS
RDY
CEZ
OEZ
CES
CAS
AVC
AVD
OE
D a t a
Synchronous Access Time
Burst Access Time Valid Clock to Output
Delay
Address Setup Time to CLK
Address Hold Time from CLK
Data Hold Time
Chip Enable to RDY Active
Output Enable to RDY Low
Chip Enable to High Z
Output Enable to High Z
CE# Setup Time to CLK
Ready Access Time from CLK
CE# Setup Time to AVD#
AVD# Low to CLK Setup Time
AVD# Pulse
Table 11.3 Synchronous Wait State Requirements
S h e e t
Description
S29WS-P
( A d v a n c e
(Note 1)
(Note 1)
Max
Max
Max
Max
Max
Max
Max
Min
Min
Min
Min
Min
Min
Min
I n f o r m a t i o n )
Wait State Requirement
54 MHz
13.5
13.5
13.5
10
10
5
6
4
4
8
BACC
S29WS-P_00_A7 November 8, 2006
2
3
4
5
6
7
8
9
66 MHz
or Clock to Out)
11.2
11.2
11.2
10
10
4
6
3
4
8
80
10
0
6
80 MHz
10
10
9
4
5
3
9
4
9
8
108 MHz
7.6
3.5
7.6
5
2
7
7
4
6
6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns