S29WS-P SPANSION [SPANSION], S29WS-P Datasheet - Page 19

• Manufacturer Part Number: S29WS-P
• Description: 512/256/128 Mb (32/16/8 M x 16 bit) 1.8 V Burst Simultaneous Read/Write MirrorBit Flash Memory
• Manufacturer: SPANSION [SPANSION]

7.3
7.4
November 8, 2006 S29WS-P_00_A7
7.4.1
Page Mode Read
Synchronous (Burst) Read Operation
Latency Tables for Variable Wait State
The device is capable of fast page mode read. This mode provides random read access speed for locations
within a page. Address bits Amax–A3 select an 8 word page, and address bits A2–A0 select a specific word
within that page. This is an asynchronous operation with the microprocessor supplying the specific word
location. It does not matter if AVD# stays low or toggles once. However, the address input must be always
valid and stable if AVD# is low during the page read.
The random or initial page access is t
locations specified by the microprocessor falls within that page) is equivalent to t
deasserted (=V
CE# selects the device and OE# is the output control and should be used to gate data to the output inputs if
the device is selected. Fast page mode accesses are obtained by keeping Amax–A3 constant and changing
A2–A0 to select the specific word within that page.
The device is capable of continuous sequential burst operation and linear burst operation of a preset length.
When the device first powers up, it is enabled for asynchronous read operations and can be automatically
enabled for burst mode. To enter into synchronous mode, the configuration register will need to be set.
Prior to entering burst mode, the system should determine how many wait states are desired for the initial
word (t
transition with valid data. The system would then write the configuration register command sequence.
Once the system has written the Set Configuration Register command sequence, the device is enabled for
synchronous reads only.
The data is output t
rising edge of each successive clock cycle, which automatically increments the internal address counter.
Note that data is output only at the rising edge of the clock. RDY indicates the initial latency.
The following tables show the latency for variable wait state in a normal Burst operation
D a t a
Word
0
1
2
3
4
5
6
7
IACC
) of each burst access, what mode of burst operation is desired and how the RDY signal will
S h e e t
Initial Wait
IH
), the reassertion of CE# for subsequent access has access time of t
9 ws
IA
Word 0
Word 1
Word 2
Word 3
Word 4
Word 5
Word 6
Word 7
Word
after the rising edge of the first CLK. Subsequent words are output t
( A d v a n c e
D0
D1
D2
D3
D4
D5
D6
D7
Table 7.3 Address Latency for 9 Wait States
ACC
1 ws
D1
D2
D3
D4
D5
D6
D7
S29WS-P
or t
Table 7.2 Page Select
I n f o r m a t i o n )
CE
1 ws
1 ws
D2
D3
D4
D5
D6
D7
and subsequent page read accesses (as long as the
A2
1 ws
1 ws
1 ws
0
0
0
0
1
1
1
1
D3
D4
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
D4
D5
D6
D7
1 ws
1 ws
1 ws
1 ws
1 ws
D5
D6
D7
A1
0
0
1
1
0
0
1
1
PACC
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D6
D7
. When CE# is
ACC
or t
BACC
CE
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
1 ws
D7
. Here again,
after the
A0
0
1
0
1
0
1
0
1
D8
D8
D8
D8
D8
D8
D8
D8
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