M41T93_11 STMICROELECTRONICS [STMicroelectronics], M41T93_11 Datasheet - Page 31

• Manufacturer Part Number: M41T93_11
• Description: Serial SPI bus real-time clock with battery switchover
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M41T93
3.8.1
Note:
3.8.2
3.8.3
3.8.4
TI/TP
●
●
If an alarm condition, watchdog time-out, oscillator failure, or OUT = 0 cause IRQ/FT/OUT to
be asserted low, then IRQ/FT/OUT will remain asserted even if TI/TP is set to '1.' When in
pulse mode (TI/TP = 1), clearing the TF bit will not stop the pulses on IRQ/FT/OUT. The
output pulses will only stop if TE, TIE, or TI/TP are reset to '0.'
Table 8.
1. TF and IRQ/FT/OUT become active simultaneously.
2. n = loaded countdown timer value. The timer is stopped when n = 0.
TF
At the end of a timer countdown, TF is set to logic '1.' If both timer and alarm interrupts are
required in the application, the source of the interrupt can be determined by reading the flag
bits. The timer will auto-reload and continue to count down regardless of the state of TF bit
(or TI/TP bit). The TF bit is cleared by reading the flags register.
TIE
In level mode (TI/TP = 0), when TF is asserted, the interrupt is asserted (if TIE = 1). To clear
the interrupt, the TF bit or the TIE bit must be reset.
TE
●
●
TI/TP = 0
IRQ/FT/OUT is active when TF is logic '1' (subject to the status of the timer interrupt
enable bit (TIE).
TI/TP = 1
IRQ/FT/OUT pulses active according to
TE = 0
When the timer register (10h) is set to ‘0,’ the timer is disabled.
TE = 1
The timer is enabled. TE is reset (disabled) on power-down. When re-enabled, the
counter will begin from the same value as when it was disabled.
Source clock (Hz)
Interrupt operation (bit TI/TP = 1)
4096
1/60
64
1
Doc ID 12615 Rev 6
n
1/8192
1/128
(2)
1/64
1/64
Table 8
= 1
(subject to the status of the TIE bit).
IRQ
(1)
period(s)
1/4096
n > 1
1/64
1/64
1/64
Clock operation
31/51