AD9287BCPZRL-100 AD [Analog Devices], AD9287BCPZRL-100 Datasheet

AD9287BCPZRL-100

Manufacturer Part Number

AD9287BCPZRL-100

Description

Quad, 8-Bit, 100 MSPS Serial LVDS 1.8 V A/D Converter

Manufacturer

AD [Analog Devices]

Datasheet

1.AD9287BCPZRL-100.pdf (52 pages)

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FEATURES

Four ADCs integrated into 1 package

133 mW ADC power per channel at 100 MSPS

SNR = 49 dB (to Nyquist)

ENOB = 7.85 bits

SFDR = 65 dBc (to Nyquist)

Excellent linearity

Serial LVDS (ANSI-644, default)

Data and frame clock outputs

295 MHz full power analog bandwidth

2 V p-p input voltage range

1.8 V supply operation

Serial port control

APPLICATIONS

Medical imaging and nondestructive ultrasound

Portable ultrasound and digital beam forming systems

Quadrature radio receivers

Diversity radio receivers

Tape drives

Optical networking

Test equipment

GENERAL DESCRIPTION

The AD9287 is a quad, 8-bit, 100 MSPS analog-to-digital

converter (ADC) with an on-chip sample-and-hold circuit that

is designed for low cost, low power, small size, and ease of use.

The product operates at a conversion rate of up to 100 MSPS

and is optimized for outstanding dynamic performance and low

power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/

CMOS-/LVDS-compatible sample rate clock for full performance

operation. No external reference or driver components are

required for many applications.

The ADC automatically multiplies the sample rate clock for the

appropriate LVDS serial data rate. A data clock (DCO) for

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

Low power reduced signal option, IEEE 1596.3 similar

DNL = ±0.2 LSB (typical)

INL = ±0.2 LSB (typical)

Full-chip and individual-channel power-down modes

Flexible bit orientation

Built-in and custom digital test pattern generation

Programmable clock and data alignment

Programmable output resolution

Standby mode

Serial LVDS 1.8 V A/D Converter

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

capturing data on the output and a frame clock (FCO) for

signaling a new output byte are provided. Individual channel

power-down is supported and typically consumes less than

2 mW when all channels are disabled.

The ADC contains several features designed to maximize

flexibility and minimize system cost, such as programmable

clock and data alignment and programmable digital test pattern

generation. The available digital test patterns include built-in

deterministic and pseudorandom patterns, along with custom user-

defined test patterns entered via the serial port interface (SPI®).

The AD9287 is available in a Pb-free, 48-lead LFCSP package. It is

specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

VIN + A

VIN – A

VIN + B

VIN – B

VIN + C

VIN – C

VIN + D

VIN – D

SENSE

REFB

VREF

REFT

Small Footprint. Four ADCs are contained in a small, space-

saving package; low power of 133 mW/channel at 100 MSPS.

Ease of Use. A data clock output (DCO) is provided that

operates up to 400 MHz and supports double data rate

operation (DDR).

User Flexibility. Serial port interface (SPI) control offers a wide

range of flexible features to meet specific system requirements.

Pin-Compatible Family. This includes the AD9219 (10-bit),

AD9228 (12-bit), and AD9259 (14-bit).

AVDD

SELECT

REF

RBIAS

FUNCTIONAL BLOCK DIAGRAM

AGND

Quad, 8-Bit, 100 MSPS

+ –

AD9287

T/H

0.5V

CSB

PDWN

SERIAL PORT

INTERFACE

SDIO/ODM

Figure 1.

PIPELINE

ADC

SCLK/DTP

DRVDD

MULTIPLIER

DATA RATE

CLK+

SERIAL

LVDS

AD9287

www.analog.com

DRGND

CLK–

D + A

D – A

D + B

D – B

D + C

D – C

D + D

D – D

FCO+

FCO–

DCO+

DCO–

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